BCD8sP: An advanced 0.16 &amp;#x03BC;m technology platform with state of the art power devices

Roggero, R.; Croce, Giuseppe; Gattari, Paolo; Castellana, E.; Molfese, A.; Marchesi, Giulio; Atzeni, Laura; Buran, C.; Палеари, А.; Ballarin, Giuseppe; Manzini, Stefano; Alagi, Filippo; Pizzo, G.

doi:10.1109/ispsd.2013.6694422

Cited by 26 publications

(13 citation statements)

References 1 publication

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“…Medium rated voltage N-drift LDMOS transistors, fabricated on 200mm-wafers by STMicroelectronics [11], are considered and shown in Fig. 1.…”

Section: Device Structure Experimental Setup and Tcad Calibrationmentioning

confidence: 99%

“…The devices under investigation feature a gate width of 20 µm, a gate oxide thickness of 12 nm, and a customized thick oxide in the N-drift region, aimed at optimizing the SOA limitations of STI architecture [11], ranging between 200 nm and 400 nm.…”

Section: Device Structure Experimental Setup and Tcad Calibrationmentioning

confidence: 99%

“…In this paper, a hot carrier degradation analysis has been performed on medium rated voltage N-drift LDMOS transistors with customized thick oxide aimed at optimizing the SOA limitations coming from the STI architecture [11]. In particular, the ONresistance degradation in linear regime has been experimentally investigated for an extended range of stress conditions and finely reproduced by means of TCAD simulations.…”

Section: Introductionmentioning

confidence: 99%

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Investigation of the hot carrier degradation in power LDMOS transistors with customized thick oxide

Tallarico

Reggiani

Magnone

et al. 2017

Microelectronics Reliability

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In this paper, we report a combined experimental/simulation analysis of the degradation induced by hot carrier mechanisms, under ON-state stress, in silicon-based LDMOS transistors. In this regime, electrons can gain sufficient kinetic energy necessary to create interface states, hence inducing device degradation. In particular, the ON-resistance degradation in linear regime has been experimentally characterized by means of different stress conditions and temperatures. The hot-carrier stress regime has been fully reproduced in the frame of TCAD simulations by using physics-based models able to provide the degradation kinetics. A thorough investigation of the spatial interface trap distribution and its gate-bias and temperature dependences has been carried out achieving a quantitative understanding of the degradation effects in the device.

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“…Medium rated voltage N-drift LDMOS transistors, fabricated on 200mm-wafers by STMicroelectronics [11], are considered and shown in Fig. 1.…”

Section: Device Structure Experimental Setup and Tcad Calibrationmentioning

confidence: 99%

Section: Device Structure Experimental Setup and Tcad Calibrationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Investigation of the hot carrier degradation in power LDMOS transistors with customized thick oxide

Tallarico

Reggiani

Magnone

et al. 2017

Microelectronics Reliability

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“…The STMicroelectronics BCD8sP [3,4] is 160 nm technology and consists of a combination of bipolar, CMOS and DMOS devices. It allows to build low voltage (1.8 V) devices featuring a high voltage (up to 70 V) insulation.…”

Section: Bcd8sp Technologymentioning

confidence: 99%

Characterization of HV-CMOS detectors in BCD8 technology and of a controlled hybridization technique

Zaffaroni¹,

Andreazza²,

Castoldi³

et al. 2017

Proceedings of the 25th International Workshop on Vertex Detectors — PoS(Vertex 2016)

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Radiation detectors built in high-voltage and high-resistivity CMOS technology are an interesting option for the large area pixel-trackers sought for the upgrade of the Large Hadron Collider experiments. A characterisation of the BCD8 technology by STMicroelectronics process has been performed to evaluate its suitability for the realisation of CMOS sensors with a depleted region of several tens of micrometer. Sensors featuring 50 × 250 µm 2 pixels on a 125 Ω cm resistivity substrate have been characterized. The response to ionizing radiation is tested using radioactive sources and an X-ray tune, reading out the detector with an external spectroscopy chain. Irradiation tests were performed up to proton fluences exceeding 5 · 10 15 p/cm 2 and they show the depletion and breakdown voltages increases with irradiation. A hybridization process for capacitive coupling has been developed. Assemblies have been performed using the ATLAS FE-I4 readout ASIC and prototype CMOS sensors. Measurements show a planarity better than 1.5 µm peak-to-peak on the 5 mm length of the HV-CMOS chip. To evaluate more precisely the achievable uniformity dummy chips of FE-I4 sizes have been made on 6-inch wafers. The measurement of the 24 capacitors on each chip is expected to achieve a precise estimation of the real thickness uniformity. The goal is to achieve less then 10% variation on the glue thickness (∼ 0.5 µm).

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“…The benchmarking data against the latest published data is shown in Fig.5 for NMOS. The low RonA version NMOS achieves state of the art RonA/BVdss tradeoff [2,5,6,7,8]. Process robustness for HV MOSFETs has been studied, to cover (1) +/-10% dose split for each implant step of drift, (2) Vth implant split of PWELL and (3) STI CD/overhead/trench depth split.…”

Section: B Hv Mosfetmentioning

confidence: 99%

A 0.18μm SOI BCD technology for automotive application

Yang¹,

Sim²,

Toner³

et al. 2015

2015 IEEE 27th International Symposium on Power Semiconductor Devices &Amp; IC's (ISPSD)

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This paper presents a new SOI BCD technology at the 0.18 m node to fulfill the requirements for smart power IC technology targeted for automotive application. Built on a 1.8V and 5.0V CMOS core, there are 40V and 60V rated N/Pch MOS, with 25m .mm 2 RonA/57V BVdss having been achieved for the 40V NMOS with excellent process stability. Depletion NMOS, LV&HV diodes, 5V zener diode, high gain BJT, excellent matching well resistor, capacitors, top thick Copper Metallization option, embedded memory (OTP, CEEPROM, etc.) are also offered on this comprehensive technology platform.

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BCD8sP: An advanced 0.16 μm technology platform with state of the art power devices

Cited by 26 publications

References 1 publication

Investigation of the hot carrier degradation in power LDMOS transistors with customized thick oxide

Investigation of the hot carrier degradation in power LDMOS transistors with customized thick oxide

Characterization of HV-CMOS detectors in BCD8 technology and of a controlled hybridization technique

A 0.18μm SOI BCD technology for automotive application

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