Behavioral Fault Modeling and Simulation Using VHDL-AMS to Speed-Up Analog Fault Simulation

Abstract

Abstract.One of the main requirements for generating test patterns for analog and mixed-signal circuits is fast fault simulation. Analog fault simulation is much slower than the digital equivalent. This is due to the fact that digital circuit simulators use less complex algorithms compared with transistor-level simulators. Two of the techniques to speed up analog fault simulation are: fault dropping/collapsing, in which faults that have similar circuit responses compared with the fault-free circuit response and/or with another faulty circuit response are considered equivalent; and behavioral/macro modeling, whereby parts of the circuit are modeled at a more abstract level, therefore reducing the complexity and the simulation time. This paper discusses behavioral fault modeling to speed-up fault simulation for analog circuits.

Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review

“…These techniques are possibly best if used in multi-level fault simulations. The idea of modeling faults at the behavioral level has been discussed in [9], [29], [31], [35], [53], [62], [66], [74], [78], [82], [89], [91] to speed up the fault simulation process.…”

“…Fault simulation using high-level models [9], [53], [91], [29], [62], [89], [82], [35], [31], [58], [66], [74], [78], [40], [87], [55], [42], [82], [91], [56] Fault simulation using fault grouping [70], [21], [48], [46], [54], [92], [65], [41], [86], [8], [25], [60] Concurrent and parallel fault simulation [7], [51], [69], [61], [37], [51], [30] Fault sensitivity analysis [11], [75], [33], [49], [26], [28] Monte Carlo simulation [10], [47], [22] DC fault simulation [64]…”

Review of high level fault modeling approaches for mixed-signal systems

“…In addition fault collapsing is also mentioned in this paper. However, only short faults are modeled and the behavioral model is only structured in HSPICE, it may be more efficient in term of speed if an HDL is employed such as VHDL-AMS [16] . However, the majority of published models have difficulties in accurately modeling some of the more nonlinear fault effects and in some cases these are dropped from the list of faults under consideration.…”

“…During the last few years, High Level Fault Modeling (HLFM) and High Level Fault Simulation (HLFS) techniques have been proposed for modern complex analogue and mixed mode system design due to its high speed [16][17][18] . Further details can be found in Section II.…”