Behavioral-level synthesis of heterogeneous BISR reconfigurable ASIC's

Abstract

Abstract-In this paper, behavioral-level synthesis techniques are presented for the design of reconfigurable hardware. The techniques are applicable for synthesis of several classes of designs, including 1) design for fault tolerance against permanent faults, 2) design for improved manufacturability, and 3) design of application specific programmable processors (ASPP's)-processors designed to perform any computation from a specified set on a single implementation platform. This paper focuses on design techniques for efficient built-in self-repair (BISR), and thus directly addresses the former two applications. Previous BISR techniques have been based on replacing a failed module with a backup of the same type. We present new heterogeneous BISR methodologies which remove this constraint and enable replacement of a module with a spare of a different type. The approach is based on the flexibility of behavioral-level synthesis to explore the design space. Two behavioral synthesis techniques are developed; the first method is through assignment and scheduling, and the second utilizes transformations. Experimental results verify the effectiveness of the approaches.

Reconfigurable high performance architectures: How much are they ready for safety-critical applications?

“…Such a software-based administration can be applied only to statically scheduled processors, e.g., VLIW processors, where the program has control over the used hardware components. Some early work on a software-based reconfiguration of a programmable application specific data path was published by Guerra [22] and Karri [23]. There, various schedules of the same program were generated in advance for different fault states of the data path.…”

Applications of Small-Scale Reconfigurability to Graphics Processors

“…They further claim that the single precision mode is particularly useful for SIMD applications, like graphics, because it is conducive to systems on which the same operation is regularly repeated on large numbers of data points. Guerra et al explore built-in-self-repair (BISR) and its application to fault tolerance, manufacturability, and application specific programmable processor design [6]. Previous work in the area of dynamic repair had made use of specialized redundant units to replace damaged units; their paper describes the synthesis of more general units that can replace any of several units on a chip when damage is detected.…”

Intellectual Property Metering

“…BISR designs are designs which have built in self repair fault tolerance that can function properly even if some parts of the design are faulty [17]. The idea here is to intentionally induce variety of faults in BISR designs in such a way that each design has different faulty parts.…”