Hardware security (HS)
RationaleIn the 70's, area emerged as the dominant synthesis and design objective for integrated circuit (IC), in the '80s the objective was speed of execution, and in the 90's it became power. While all these objectives are still very important, security, privacy, and digital right management (DRM) arise as the most important metrics in many modern and emerging applications [7]. The paradigm shift toward DRM, security and privacy is not only due to the common impact of technology push and applications pool, but also it is a consequence of an inherently insecure but dominant horizontal microelectronic business model and design reuse. The horizontal model is where the design houses, silicon foundries, and system integrators are economically separate entities; hardware IP reuse is to alleviate the design productivity gap.In preparing students for designing secure hardware, the most challenging is that the intrinsic nature and concepts needed for ensuring security are sharply different from the ones for area, speed, or power optimization. In addition, HS has close interactions with the underlying technologies, system software, and applications. Another significant hurdle is that a high percentage of students do not have a solid background in security.Our strategic goal is to prepare students for synthesis and evaluation of secure devices and systems. The main technical objectives of the course include understanding of security and DRM mechanisms such as non-destructive observability, IC uniqueness, and methods for hiding information inside the design specifications. A special focus is placed on sound foundation and complete coverage of attacks -defense mechanisms and protocols -, and analysis and complete understanding of the assumptions and models. We also emphasize the importance of preserving transparency of the synthesis process in realizing the HS features.
TopicsIn the offerings so far, we covered in technical details various subsets of the following topics: (i) smart cards; (ii) manufacturing variability and HW security; (iii) watermarking of designs; (iv) IC fingerprinting; (v) IC metering (vi) HW Trojan horse detection; (vii) IC rapid aging attacks that exploit HCI (hot carrier induced degradation), TDDB (time dependent dielectric [soft/hard] breakdown) and NBTI (negative bias temperature instability) deepsubmicron transistor degradation and interconnect electromigration. (viii) obfuscation of the specification of designs and nonreadability of data and computation against power, delay, and radiation attacks; (ix) physically unclonable functions; (x) secure coprocessor, algorithmic HW attacks, and buffer overflow attacks; (xi) HW identification using clock skew and manufacturing variability techniques; (xii) voting HW; (xiii) biometrics techniques and HW; (xiv) jamming and time synchronization attacks in wireless networks; (xv) explosives, chemical, and biologic toxic material detection; and (xvi) security of physical objects such as locks and digital IDs. We briefly elabor...