Behavioral modeling of switched-capacitor sigma-delta modulators

Abstract

This paper presents a complete set of blocks implemented in the popular MATLAB SIMULINK environment, which allows designers to perform time-domain behavioral simulations of switched-capacitor (SC) sigma-delta (61) modulators. The proposed set of blocks takes into account most of the SC 61 modulator nonidealities, such as sampling jitter, noise, and operational amplifier parameters (white noise, finite dc gain, finite bandwidth, slew rate and saturation voltages). For each block, a description of the considered effect as well as all of the implementative details are provided. The proposed simulation environment is validated by comparing the simulated behavior with the experimental results obtained from two actual circuits, namely a second-order low-pass and a sixth-order bandpass SC 61 modulator.

A High-Speed Delta-Sigma Modulator with Relaxed DEM Timing Requirement

“…To demonstrate the validity of removing DAC linearization (DEM) in the main DAC, three 3 rd order Ms are simulated using the MATLAB/Simulink ® model [11], [12] under various conditions: one analog feed-forward M [7] as a reference and two digital feed-forward Ms as illustrated in Fig. 6, one with a 4b auxiliary quantizer and the other with a 5b auxiliary quantizer.…”

Multi-stage sigma-delta ADC with noise-coupling technology

“…The non-ideal factors, such as clock jitter, thermal noise, and opamp finite gain, were considered and simulated as shown in Fig. 3(a) [7]. The various parameters of these modules need to be chosen reasonably to simulate the actual circuit conditions effectively.…”

Evaluation of the Delta-Sigma Modulator Coeficients by MATLAB Parallel Processing

“…It is very universal tool and the result of the calculation is value of SNDR (Malcovati et al, 2003). On the other hand, it is not able to differ contribution of particular errors on spurious free dynamic range SFDR…”