This paper presents a complete set of blocks implemented in the popular MATLAB SIMULINK environment, which allows designers to perform time-domain behavioral simulations of switched-capacitor (SC) sigma-delta (61) modulators. The proposed set of blocks takes into account most of the SC 61 modulator nonidealities, such as sampling jitter, noise, and operational amplifier parameters (white noise, finite dc gain, finite bandwidth, slew rate and saturation voltages). For each block, a description of the considered effect as well as all of the implementative details are provided. The proposed simulation environment is validated by comparing the simulated behavior with the experimental results obtained from two actual circuits, namely a second-order low-pass and a sixth-order bandpass SC 61 modulator.

This paper presents a complete set of SIMULINK@ models, which allow exhaustive behavioral simulations of any sigma-delta modulator to be performed. The proposed set of models takes into account most of the sigma-delta modulator non-idealities, such as sampling jitter, kT/C noise and operational amplifier parameters (noise, finite gain, finite bandwidth, slew-rate and saturation voltages). For each model we present a description of the considered effect as well as all of the implementative details. Simulation results on a second-order switched-capacitor sigma-delta modulator demonstrate the validity of the models proposed.

Abstract-In this paper, we present a switched-capacitor sigmadelta (6-1) modulator for high resolution applications. In particular, this 6-1 modulator is well suited for distributed sensor networks. The circuit, implemented in a double-poly, double-metal 0.6 m CMOS technology, is based on a fourth-order single-loop architecture with a sampling frequency of 256 kHz. The chip consumes 50 mW from a single 5-V supply and achieves a signal-tonoise ratio of 104.9 dB over a bandwidth of 400 Hz, corresponding to a resolution of 17.1 bits.

No abstract

This paper presents a set of SIMULINK models and MATLAB files, which allow exhaustive behavioral simulations of Fractional4 division frequency synthesizers based on PLL. The proposed set of models takes into account most of PLL's non-idealities. For each model we present a description of the considered effect as well as all of the implementative details. Simulation results on a Fractional-N division frequency synthesizer based on PLL demonstrate the validity of the models proposed.