Modeling of fractional-N division frequency synthesizers with SIMULINK and MATLAB

Brigati, S.; Francesconi, F.; Malvasi, Angelo; Pesucci, A.; Poletti, M.

doi:10.1109/icecs.2001.957685

Cited by 15 publications

(6 citation statements)

References 3 publications

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“…9 Following the above classical consideration, the filter is often represented in MatLab Simulink as the block Transfer Fcn with zero initial state (see, e.g. [35]- [39]). It is also related to the fact that the transfer function (from ϕ to g) of linear system (2) is defined by the Laplace transformation for zero initial data x(0) ≡ 0.…”

Section: Definition 1 a Set Of All Frequency Deviations |ω Free ∆ | mentioning

confidence: 99%

Hold-In, Pull-In, and Lock-In Ranges of PLL Circuits: Rigorous Mathematical Definitions and Limitations of Classical Theory

Леонов

Kuznetsov

Yuldashev

et al. 2015

IEEE Trans. Circuits Syst. I

123

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Abstract-The terms hold-in, pull-in (capture), and lock-in ranges are widely used by engineers for the concepts of frequency deviation ranges within which PLL-based circuits can achieve lock under various additional conditions. Usually only non-strict definitions are given for these concepts in engineering literature. After many years of their usage, F. Gardner in the 2nd edition of his well-known work, Phaselock Techniques, wrote "There is no natural way to define exactly any unique lock-in frequency" and "despite its vague reality, lock-in range is a useful concept". Recently these observations have led to the following advice given in a handbook on synchronization and communications "We recommend that you check these definitions carefully before using them" [1, p.49]. In this survey an attempt is made to discuss and fill some of the gaps identified between mathematical control theory, the theory of dynamical systems and the engineering practice of phase-locked loops. It is shown that, from a mathematical point of view, in some cases the hold-in and pull-in "ranges" may not be the intervals of values but a union of intervals and thus their widely used definitions require clarification. Rigorous mathematical definitions for the hold-in, pullin, and lock-in ranges are given. An effective solution for the problem on the unique definition of the lock-in frequency, posed by Gardner, is suggested.Index Terms-Phase-locked loop, nonlinear analysis, analog PLL, high-order filter, local stability, global stability, stability in the large, cycle slipping, hold-in range, pull-in range, capture range, lock-in range, definition, Gardner's problem on unique lock-in frequency, Gardner's paradox on lock-in range.

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Section: Definition 1 a Set Of All Frequency Deviations |ω Free ∆ | mentioning

confidence: 99%

Hold-In, Pull-In, and Lock-In Ranges of PLL Circuits: Rigorous Mathematical Definitions and Limitations of Classical Theory

Леонов

Kuznetsov

Yuldashev

et al. 2015

IEEE Trans. Circuits Syst. I

123

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“…These drawbacks create harmonics at the output of the frequency synthesizer every multiple of the reference frequency. The magnitude of these harmonics increases as the mismatching and the leakage current increase [4]. This is why a special care is taken in the design of charge-pump stage in frequency synthesizer [3].…”

Section: B Advantage Of Using a Type I Frequency Synthesizermentioning

confidence: 98%

Modeling and optimization of a dedicated FMCW radar frequency synthesizer

Avignon-Meseldzija¹,

Azarian²,

Font³

et al. 2013

2013 European Conference on Circuit Theory and Design (ECCTD)

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International audienceDownload Citation Email Print Request Permissions Save to Project This paper presents the modeling and optimization of a frequency synthesizer dedicated to FMCW radar applications. This frequency synthesizer based on a type-I PLL presents the advantages of a simplified architecture with less potential electronic drawbacks. A methodology to optimize the filter loop is proposed in order to obtain the required smoothed frequency characteristic and correct the VCO distortion

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“…1 is simulated using Hspice. To overcome the inherent problems [7] of transistor level simulation of the fractional-N PLL as a whole system, behavioral simulation approach is introduced to check the functionality of the proposed fractional-N synthesizer. All the blocks including PFD, LPF, VCO, prescaler and counters are modeled at function level using expressions and behavioral modeling features of Hspice.…”

Section: Prototype Developmentmentioning

confidence: 99%

A Novel Architecture for Programmable Fractional-N PLL

Rana

2006

Analog Integr Circ Sig Process

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In this paper, a novel architecture for programmable fractional-N PLL is proposed. Unlike the conventional fractional-N PLL, it does not need any input data word to meet step size requirement. It features programmability in step sizes. The ratio of the externally controlled counter values sets the step size and thus step size is not limited by fixed hardware. A flow chart is provided to understand the operation of the various counters used in the proposed architecture. A behavioral modeling approach is attempted to perform overall system simulation using Hspice. A 2.4 GHz fractional-N PLL prototype is demonstrated using 0.35 µm CMOS process and test results are provided. It has step sizes of the values of integer multiples of 50 kHz. The main contributions include: (i) Novel architecture, and (ii) Prototype implementation, all for programmable fractional-N PLL. Unlike the most PLLs, the proposed PLL system is amenable to behavioral system simulation using Hspice.

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Modeling of fractional-N division frequency synthesizers with SIMULINK and MATLAB

Cited by 15 publications

References 3 publications

Hold-In, Pull-In, and Lock-In Ranges of PLL Circuits: Rigorous Mathematical Definitions and Limitations of Classical Theory

Hold-In, Pull-In, and Lock-In Ranges of PLL Circuits: Rigorous Mathematical Definitions and Limitations of Classical Theory

Modeling and optimization of a dedicated FMCW radar frequency synthesizer

A Novel Architecture for Programmable Fractional-N PLL

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