Behavioral synthesis of fault secure controller/datapaths using aliasing probability analysis

Abstract

AbstractÐThis paper addresses the problem of synthesizing fault-secure controller/data path circuits from behavioral specifications. These circuits are guaranteed to either produce the correct output, or to flag an error. We use an iterative improvement-based behavioral synthesis framework that performs functional unit selection, clock selection, scheduling, and resource sharing with the aim of minimizing the area of the synthesized circuit, while allowing multicycling, chaining, and functional unit pipelining. We present a dynamic comparison selection algorithm that can be used during behavioral synthesis to determine which intermediate results in the computation need to be secured in order to enable maximal resource sharing. Previous work on synthesizing fault-secure data paths has focused on ensuring that aliasing (a condition when the circuit produces an incorrect output and does not flag an error) cannot occur in any part of the design. We demonstrate that such an approach can lead to unnecessarily large overheads. In order to alleviate the overheads incurred for fault security, our behavioral synthesis framework uses ALiasing Probability analysiS (ALPS) in order to identify resource sharing configurations that reduce area while introducing a very low probability of aliasing (of the order of IH ÀIH for a bit-width of 32) in the resultant data path. Experimental results performed for several behavioral descriptions demonstrate that our techniques synthesize more compact circuits than techniques available in the literature, e.g., double moIdular redundancy or zeroaliasing techniques.

Introspection

“…Straightforward duplication of a computation followed by comparison entails substantial hardware overhead. Area-efficient fault-detection strategy by comparing carefully selected intermediate results has been presented in Karri and Orailoǧlu [1996] and Lakshminarayana et al [1996]. An area-efficient technique for reconfiguration has been presented in Iyer et al [1995].…”

Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique

“…Karri and Iyer presented an RTL CED technique that uses the spare computation cycles of the functional units and the spare data transfer cycles in the interconnection network for CED [11]. Karri and Orailoglu [12] and Jha et al [14] presented CED techniques that yield fault-secure data paths with less than proportional increase in hardware. These techniques selectively check intermediate results in a control data flow graph (CDFG) of a computation and weaken some data precedence constraints and reduce hardware overhead without violating the time constraints.…”

Selectively breaking data dependences to improve the utilization of idle cycles in algorithm level re-computing data paths

“…Karri and Iyer presented a RT level CED technique that uses the spare computation cycles and the spare data transfer cycles for CED [12]. Karri & Orailoglu [13], and Lakshminarayana et al [14] presented fault security based techniques which yield CED data paths with less than a proportional increase in hardware.…”