Benchmarking and optimization of trench-based multi-gate transistors in a 40 nm non-volatile memory technology

Abstract

This paper addresses the design and characterization of different architectures of novels highdensity multi-gate transistors manufactured in a 40 nm embedded Non-Volatile Memory technology. The proposed multi-gate architectures are based on vertical transistors integrated in deep trenches built alongside the main transistor. Thanks to the built-in trench, the proposed manufacturing process increases the transistor width without impacting its footprint. The electrical behaviour of the different multi-gate transistor architectures is studied and compared based on I-V characteristics. Relevant physical and electrical parameters such as the device footprint, the ON and OFF currents along with the threshold voltage and subthreshold slopes are extracted in order to determine the best candidate among the three studied architectures.

AC stress analysis of trench-based multi-gate transistors in a 40 nm e-NVM technology

“…The aim of this section is to study the behaviour of the different multi-gate devices under AC gate stress. The quasistatic drain current versus gate voltage, characteristics are reported in a previous work [16], where we benchmarked our MGT architectures in terms of single device performances. As these have similar architecture of FinFET transistor, we report here some electrical parameters to compare these two devices with similar dimensions we refer to [18] and [19].…”

“…As these have similar architecture of FinFET transistor, we report here some electrical parameters to compare these two devices with similar dimensions we refer to [18] and [19]. From [16] we calculate the normalized: ON current (ION), OFF current (IOFF) and subthreshold slope (Ss), using a vertical channel width of 50nm. This last depends on source/drain implantations.…”

“…On the contrary the planar conduction is immune from the lateral stress, taking advantage from the lower height of vertical trenches with respect to the planar active region. Finally, the DGT architecture is the best candidate regarding the electrical performances [16] and the reliability results. A benchmark of experimental results is summarized in Table II.…”

“…These multi-gate structures have been fabricated to improve the driving capability with a low impact on the area of planar transistors used in column decoders to address the memory cells. A description of the functioning and performances of these devices are presented in [15] [16]. The MGT architecture design is based on a typical planar MOS transistor to which two lateral conduction channels are added by integrating deep trench transistors alongside the planar one between source and drain regions.…”