Bended Gate-All-Around Nanowire MOSFET: a device with enhanced carrier mobility due to oxidation-induced tensile stress

Moselund, Kirsten E.; Dobrosz, P.; Olsen, SH; Pott, V.; Michielis, L. De; Tsamados, Dimitrios; Bouvet, D.; O'Neill, AG; Ionescu, Adrian M.

doi:10.1109/iedm.2007.4418899

Cited by 36 publications

(25 citation statements)

References 3 publications

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“…The volume expansion of the oxide during thermal oxidation has long been known to induce strain in silicon, and this has been shown to enhance the transconductance [7] and mobility in silicon nanowires [8], [9]. Normally, one would expect a relaxation of the strain to take place once the straining oxide layer is removed; hence, most studies investigate the strain effects while maintaining the oxide.…”

Section: A Thermal Oxidation As Strain-inducing Techniquementioning

confidence: 99%

The High-Mobility Bended n-Channel Silicon Nanowire Transistor

Moselund

Najmzadeh

Dobrosz

et al. 2010

IEEE Trans. Electron Devices

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Abstract-This work demonstrates a method for incorporating strain in silicon nanowire gate-all-around (GAA) n-MOSFETs by oxidation-induced bending of the nanowire channel and reports on the resulting improvement in device performance. The variation in strain measured during processing is discussed. The strain profile in silicon nanowires is evaluated by Raman spectroscopy both before device gate stack fabrication (tensile strains of up to 2.5% are measured) and by measurement through the polysilicon gate on completed electrically characterized devices. Drain current boosting in bended n-channels is investigated as a function of the transistor operation regime, and it is shown that the enhancement depends on the effective electrical field. The maximum observed electron mobility enhancement is on the order of 100% for a gate bias near the threshold voltage. Measurements of stress through the full gate stack and experimental device characteristics of the same transistor reveal a stress of 600 MPa and corresponding improvements of the normalized drain current, normalized transconductance, and low-field mobility by 34% (at maximum gate overdrive), 50% (at g max ), and 53%, respectively, compared with a reference nonstrained device at room temperature. Finally, it is found that, at low temperatures, the low-field mobility is much higher in bended devices, compared with nonbended devices.

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Section: A Thermal Oxidation As Strain-inducing Techniquementioning

confidence: 99%

The High-Mobility Bended n-Channel Silicon Nanowire Transistor

Moselund

Najmzadeh

Dobrosz

et al. 2010

IEEE Trans. Electron Devices

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“…We assume that the difference between our results and the reported results on µ eff is due to a deposited thick gate oxide, which retards the electrical field near corners because of a structural relaxation of the corner sharpness by deposition, not by thermal oxidation. Another possible reason could be the strong stress because of the SiN hard mask, which resulted in a bended SiNW channel in [4,25].…”

Section: Tables 1 and 2)mentioning

confidence: 99%

“…Therefore, smoothing technologies, such as hydrogen annealing [7] and hydrogen thermal etching [8], have also been proposed for rounding the SiNW channel or etching the LER of the SiNW channel. As a result, there exist various cross-sectional shapes of the SiNW channels: triangular [2,4], circular [1], ellipsoidal [9], and rectangular [10]. The effects of the various cross-sectional shapes of the SiNW FETs on their electrical properties have been reported, for example, the gate capacitance [11], the on-current I ON [12], the threshold voltage (V th ) [13], the effective carrier mobility (µ eff ) [14], and the interfacial state density (D it ) [15].…”

Section: Introductionmentioning

confidence: 99%

“…The cross-sectional shapes of the SiNW channel depend on the initial shape and dimensions of silicon fins and additional thermal oxidation process conditions [3]. The initial shape is usually rectangular and can be modified with anisotropic dry etching with SiN hard mask [4]. Oxidation temperature, time, dopant concentration and ambient (dry or wet) affect the cross-sectional shape of the fabricated SiNW because stress in sacrificial silicon oxide, which surrounds the SiNW channel during the process, is highly significant for determining the cross-sectional shape of the SiNW channel [5].…”

Section: Introductionmentioning

confidence: 99%

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Effects of corner angle of trapezoidal and triangular channel cross-sections on electrical performance of silicon nanowire field-effect transistors with semi gate-around structure

Sato

Kakushima

Ahmet

et al. 2011

Solid-State Electronics

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Structural effects, especially corner angle of upper-corners of trapezoidal and rectangular, and triangular cross-sectional shapes of silicon nanowire field-effect transistors on effective carrier mobility and normalized inversion charge density have been investigated. <100>-directed silicon nanowire field-effect transistors with semi-gate around structure fabricated on (100)-oriented silicon-on-insulator wafers were evaluated. As the upper-corner angle decreased from obtuse to acute angle, we observed an increased amount of inversion charge using split-CV measurement. On the other hand, the effective carrier mobility dependence on the upper-corner angle seems to have an optimized point near 100 o at 296 K. Although normalized inversion charge density was the largest with acute angles, effective carrier mobility with acute upper-corner angle was severely degraded.Considering the intrinsic delay time of SiNW FET, SiNW FETs with trapezoidal cross-section with upper-corner angle of 100 o is more suitable in this work to achieve high electrical performance. We believe these findings could represent guidelines for the design of high-performance SiNW FETs.

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“…The increasing costs of photolithography motivates the development of lithography-independent nanowire (NW) fabrication processes. These techniques can be divided into bottom-up approaches based on SiNW growth from a catalyst [1] and top-down approaches based on the accurate control of etching and oxidation of Si [2] and deposition of poly-Si [3], [4] (for SiNW and polySiNW, respectively).…”

mentioning

confidence: 99%

Polysilicon Nanowire Transistors and Arrays Fabricated With the Multispacer Technique

Jamaa

Cerofolini

Micheli

et al. 2011

IEEE Trans. Nanotechnology

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Abstract-In this paper, we demonstrate the ability of the multispacer patterning technique to yield layers of polycrystalline silicon nanowires with a sublithographic pitch, by exclusively using micrometer resolution andCMOS processing steps. We characterize single spacers operating as poly-Si nanowire field effect transistors . We demonstrate also the possibility to lay a spacer perpendicularly to a set of parallel spacers in a crossbar fashion. The extrapolated cross-point density from the small 4 × 1-array is in the range of 10 10 cm −2 . We discuss the applications of this technique to improve the density of previously reported poly-SiNW memories and as a future framework for nanowire crossbars and decoders. Then we analyze the limitations and costs of the proposed technique.

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Bended Gate-All-Around Nanowire MOSFET: a device with enhanced carrier mobility due to oxidation-induced tensile stress

Abstract: In this paper we investigate the mobility enhance-

Cited by 36 publications

References 3 publications

The High-Mobility Bended n-Channel Silicon Nanowire Transistor

The High-Mobility Bended n-Channel Silicon Nanowire Transistor

Effects of corner angle of trapezoidal and triangular channel cross-sections on electrical performance of silicon nanowire field-effect transistors with semi gate-around structure

Polysilicon Nanowire Transistors and Arrays Fabricated With the Multispacer Technique

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