BEOL Based RRAM with one extra-mask for low cost, highly reliable embedded application in 28 nm node and beyond

Lv, Hangbing; Xu, Xiaoxin; Yuan, Peng; Dong, Danian; Gong, Tiancheng; Liu, Jing; Yu, Zhibin; Huang, Peng; Kun, Zhang; Huo, Changxing; Chen, Chanbing; Xie, Yurong; Luo, Qing; Long, Shibing; Liu, Qi; Kang, Jinfeng; Yang, Die; Yin, Simon; Chiu, Shengfen; Liu, Ming

doi:10.1109/iedm.2017.8268312

Cited by 40 publications

(13 citation statements)

References 1 publication

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“…The next-generation memory should be ultrafast as a static random access memory (SRAM) and possess non-volatility and high-density as a flash memory 4 , to overcome the large storage performance gap between different levels of the memory hierarchy. Of all the potential candidates, including phase-change RAM (PCRAM) 5,6 , magnetoresistive RAM (MRAM) 7,8 , and resistive RAM (ReRAM) 9,10 , a recently developed non-volatile resistive-type memory based on ferroelectric tunnel junction (FTJ) shows special advantages [11][12][13][14] . Especially, the write current density of an FTJ is as low as 10 3 -10 4 A cm −2 , while the typical values are about 10 6 A cm −2 in the former three types of memories.…”

mentioning

confidence: 99%

Sub-nanosecond memristor based on ferroelectric tunnel junction

et al. 2020

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Next-generation non-volatile memories with ultrafast speed, low power consumption, and high density are highly desired in the era of big data. Here, we report a high performance memristor based on a Ag/BaTiO 3 /Nb:SrTiO 3 ferroelectric tunnel junction (FTJ) with the fastest operation speed (600 ps) and the highest number of states (32 states or 5 bits) per cell among the reported FTJs. The sub-nanosecond resistive switching maintains up to 358 K, and the write current density is as low as 4 × 10 3 A cm −2. The functionality of spike-timingdependent plasticity served as a solid synaptic device is also obtained with ultrafast operation. Furthermore, it is demonstrated that a Nb:SrTiO 3 electrode with a higher carrier concentration and a metal electrode with lower work function tend to improve the operation speed. These results may throw light on the way for overcoming the storage performance gap between different levels of the memory hierarchy and developing ultrafast neuromorphic computing systems.

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confidence: 99%

Sub-nanosecond memristor based on ferroelectric tunnel junction

et al. 2020

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“…A TaOx switching layer was formed in the trench of M1 in connection with CT. An interface layer with a thickness of 1.5 nm∼5 nm was formed between the TaOx layer and TE. The detailed process flow of the RRAM device can be found in our previous work [14]. Figure 2c illustrates the typical DC I-V characteristics of the RRAM cell measured at room temperature, demonstrating a low 80 µ A switching current and a low operation voltage below 1.5 V. During the DC test, the bias voltage of the transistor (NMOS) is 1.4 V due to the need for current limiting protection of the RRAM device during the set operation, while the SL is grounded, and the BL provides different DC voltages.…”

Section: Trng Based On Rrammentioning

confidence: 99%

Probabilistic Circuit Implementation Based on P-Bits Using the Intrinsic Random Property of RRAM and P-Bit Multiplexing Strategy

Liu

Qiao

et al. 2022

Micromachines

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Probabilistic computing is an emerging computational paradigm that uses probabilistic circuits to efficiently solve optimization problems such as invertible logic, where traditional digital computations are difficult to solve. This paper proposes a true random number generator (TRNG) based on resistive random-access memory (RRAM), which is combined with an activation function implemented by a piecewise linear function to form a standard p-bit cell, one of the most important parts of a p-circuit. A p-bit multiplexing strategy is also applied to reduce the number of p-bits and improve resource utilization. To verify the superiority of the proposed probabilistic circuit, we implement the invertible p-circuit on a field-programmable gate array (FPGA), including AND gates, full adders, multi-bit adders, and multipliers. The results of the FPGA implementation show that our approach can significantly save the consumption of hardware resources.

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“…Low HRS/LRS ratio can become a potential problem for 2T2R gate operation since voltage drop over RRAM in LRS becomes comparable to RRAM in HRS. However, with RRAM resistance ratio up to 10 2 or 10 3 [32,33], correctness of the logic operations can be guaranteed. Lifetime of this 2T2R logic gate is also dependent upon endurance of RRAM, for which the best performance is reported to be 10 12 cycle [31].…”

Section: Op4: P' = Q→p (Imp) and Q'= P•q (And)mentioning

confidence: 99%

Scalable 2T2R Logic Computation Structure: Design From Digital Logic Circuits to 3-D Stacked Memory Arrays

Yang

Pan

Zhou

et al. 2022

IEEE J. Explor. Solid-State Comput. Devices Circuits

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In the post Moore era, post-CMOS technologies have received intense interests for possible future digital logic applications beyond the CMOS scaling limits. In the meantime, from the system perspective, non-von-Neumann architectures such as processing-in-memory (PIM) are extensively explored to overcome the bottleneck of modern computers, known as the memory wall, for high-performance energy-efficient integrated circuits. In this paper, we propose functionally complete nonvolatile logic gates based on a 2-transistor-2-RRAM (2T2R) unit structure, which is then used to form a reconfigurable 3transistor-2-RRAM (3T2R) chain with programmable interconnects for complex combinational logic circuits, and a dense 3-dimensional (3-D) stacked memory array architecture. The design has a highly regular and symmetric structure, while operations are flexible yet simple, without the need of complicated peripheral circuitry or a third resistive state. Implementations of XNOR gate and full-adder using 3T2R chain without extra routing/control gates or resistors are shown as demonstration examples of arithmetic unit design. The proposed computing scheme is intrinsic, efficient with superior performance in speed and area. Easily integrated as 3-D stacked array, the proposed memory architecture not only serves as regular 3-D memory array but also performs logic computation within the same layer and between the stacked layers. Concurrent computations under multiple computation modes for flexible operations in the memory are presented. Bias schemes for selected/half-selected/unselected cells are also explained and verified.

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BEOL Based RRAM with one extra-mask for low cost, highly reliable embedded application in 28 nm node and beyond

Cited by 40 publications

References 1 publication

Sub-nanosecond memristor based on ferroelectric tunnel junction

Sub-nanosecond memristor based on ferroelectric tunnel junction

Probabilistic Circuit Implementation Based on P-Bits Using the Intrinsic Random Property of RRAM and P-Bit Multiplexing Strategy

Scalable 2T2R Logic Computation Structure: Design From Digital Logic Circuits to 3-D Stacked Memory Arrays

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