Real time electricity monitoring is critical to enable intelligent and customized energy management for users in residential, educational, and commercial buildings. This paper presents the design, integration, and testing of a simple, self-contained, low-power, non-invasive system at low cost applicable for such purpose. The system is powered by piezoelectric energy harvesters (EHs) based on PZT and includes a microcontroller unit (MCU) and a central hub. Real-time information regarding the electricity consumption is measured and communicated by the system, which ultimately offers a dependable and promising solution as a wireless sensor node. The dynamic power management ensures the system to work with different types of PZT EHs at a wide range of input power. Thus, the system is robust against fluctuation of the current in the electricity grid and requires minimum adjustment if EH unit requires exchange or upgrade. Experimental results demonstrate that this unit is in a position to read and transmit 60 Hz alternating current (AC) sensor signals with a high accuracy no less than 91.4%. The system is able to achieve an operation duty cycle from <1 min up to 18 min when the current in an electric wire varies from 7.6 A to 30 A, depending on the characteristics of different EHs and intensity of current being monitored.
In the post Moore era, post-CMOS technologies have received intense interests for possible future digital logic applications beyond the CMOS scaling limits. In the meantime, from the system perspective, non-von-Neumann architectures such as processing-in-memory (PIM) are extensively explored to overcome the bottleneck of modern computers, known as the memory wall, for high-performance energy-efficient integrated circuits. In this paper, we propose functionally complete nonvolatile logic gates based on a 2-transistor-2-RRAM (2T2R) unit structure, which is then used to form a reconfigurable 3transistor-2-RRAM (3T2R) chain with programmable interconnects for complex combinational logic circuits, and a dense 3-dimensional (3-D) stacked memory array architecture. The design has a highly regular and symmetric structure, while operations are flexible yet simple, without the need of complicated peripheral circuitry or a third resistive state. Implementations of XNOR gate and full-adder using 3T2R chain without extra routing/control gates or resistors are shown as demonstration examples of arithmetic unit design. The proposed computing scheme is intrinsic, efficient with superior performance in speed and area. Easily integrated as 3-D stacked array, the proposed memory architecture not only serves as regular 3-D memory array but also performs logic computation within the same layer and between the stacked layers. Concurrent computations under multiple computation modes for flexible operations in the memory are presented. Bias schemes for selected/half-selected/unselected cells are also explained and verified.
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