Beyond TCAMs: An SRAM-Based Parallel Multi-Pipeline Architecture for Terabit IP Lookup

Abstract

Abstract-Continuous growth in network link rates poses a strong demand on high speed IP lookup engines. While Ternary Content Addressable Memory (TCAM) based solutions serve most of today's high-end routers, they do not scale well for the next-generation [1]. On the other hand, pipelined SRAMbased algorithmic solutions become attractive. Intuitively multiple pipelines can be utilized in parallel to have a multiplicative effect on the throughput. However, several challenges must be addressed for such solutions to realize high throughput. First, the memory distribution across different stages of each pipeline as well as across different pipelines must be balanced. Second, the traffic on various pipelines should be balanced.In this paper, we propose a parallel SRAM-based multipipeline architecture for terabit IP lookup. To balance the memory requirement over the stages, a two-level mapping scheme is presented. By trie partitioning and subtrie-to-pipeline mapping, we ensure that each pipeline contains approximately equal number of trie nodes. Then, within each pipeline, a fine-grained node-to-stage mapping is used to achieve evenly distributed memory across the stages. To balance the traffic on different pipelines, both pipelined prefix caching and dynamic subtrie-topipeline remapping are employed. Simulation using real-life data shows that the proposed architecture with 8 pipelines can store a core routing table with over 200K unique routing prefixes using 3.5 MB of memory. It achieves a throughput of up to 3.2 billion packets per second, i.e. 1 Tbps for minimum size (40 bytes) packets.

Multi-terabit ip lookup using parallel bidirectional pipelines

“…The former requires periodic reconstruction of the entire routing table, which is impractical for SRAM-based pipeline solutions due to the high overhead of updating. On the other hand, because of Internet traffic locality, IP/prefix caching is effective for speeding up the lookup throughput [7]. However, due to caching and queuing, packets within a flow may go out of order.…”

“…Although TCAM-based engines can retrieve IP lookup results in just one clock cycle, their throughput is limited by the relatively low clock rate of TCAMs. TCAMs are expensive and offer little flexibility to adapt to new addressing and routing protocols [7]. As shown in Table 1, SRAMs outperform TCAMs with respect to speed, density and power consumption.…”

Offset addressing approach to memory-efficient IP address lookup

“…Hash-based schemes [2][3][12][13][14][15][16][17] have been proposed to accelerate the IP lookup, but they require prohibitive amount of high-bandwidth memory that impedes their use in practice. Trie-based schemes [18][19][20][21][22][23][24][25][26] have been widely used in high-speed Internet routers due to their efficient data structures. Nowadays virtual routers and software routers require efficient trie-based schemes for the performance and scalability.…”

“…This makes these algorithms not keep up with the high speeds. To improve the lookup throughput of trie-based algorithms, memory pipelines [24][25][26] have been proposed to produce one lookup result per clock cycle. As on-chip memory is still small and expensive, the pipeline stages require the compact trie data structure.…”

Scalable Packet Classification: Cutting or Merging?

“…However, as shown in [8]- [10], TCAMs are not scalable with respect to clock rate, power consumption, or circuit area, compared to static random access memories (SRAMs). Most of TCAM-based solutions also suffer from range expansion when converting ranges into prefixes [3], [4].…”