Bi-directional Sub-60mV/dec, Hysteresis-Free, Reducing Onset Voltage and High Speed Response of Ferroelectric-AntiFerroelectric Hf_0.25Zr_0.75O₂ Negative Capacitance FETs

Excellent Reliability and High-Speed Antiferroelectric HfZrO2 Tunnel Junction by a High-Pressure Annealing Process and Built-In Bias Engineering

“…They concluded that ZrO 2 -based energy devices show excellent energy storage density and efficiency because of the superior breakdown field strength of ZrO 2 . Lee et al introduced a quasi-antiferroelectric Hf 0.75 Zr 0.25 O 2 (QAFE-HZO) negative capacitance (NC) field-effect transistor (FET) . Using QAFE-HZO, which exhibits a small but nonzero remnant polarization value, we can obtain FETs with the reduced NC onset voltage, hysteresis-free I – V characteristics, and fast switching properties.…”

“…17 field-effect transistor (FET). 24 Using QAFE-HZO, which exhibits a small but nonzero remnant polarization value, we can obtain FETs with the reduced NC onset voltage, hysteresis-free I−V characteristics, and fast switching properties. However, even with the benefits of AFE, we cannot use it directly for nonvolatile memory applications because it does not show any polarization without an external field, resulting in a loss of the stored information.…”

Junction Design and Complementary Capacitance Matching for NCFET CMOS Logic

“…There is no source/drain flaring, to remove any impact of 2-D fringing fields, which does not aid fundamental learning here. The L-K parameters are unbound to any particular material demonstrated in practice (although within range [2], [3], [5], [7]), in order to independently evaluate the impact of remnant polarization (Pr by varying γ, being higher as γ drops) and CNC (by varying α, being higher as |α| drops) on NCFET design and performance. It is emphasized that FE εr = 17 and TFE = 4 nm is electrostatically equivalent to εr = 34 and TFE = 8 nm, which is more in line with FE layers having large Pr [2] but requires fewer TCAD mesh points.…”

“…EGATIVE capacitance field effect transistors (NCFETs) have received attention [1][2][3][4][5][6] for their potential to extend CMOS scaling by improving electrostatic integrity and, in some cases [6][7][8], achieving sub-kT subthreshold swing (SS). The expectation for NCFETs is to achieve enhanced, high speed switching capability with zero or near-zero hysteresis (i.e., for logic applications), unlike FEFETs which specifically target hysteretic switching (i.e., for memory applications).…”

“…[11] proposed a multi-layer ferroelectric/dielectric (FE/DE) stack, with each FE layer possessing a different negative capacitance (NC) slope, in order to achieve said matching; however, SS reduction in the deep off-state is modest. [7] demonstrated non-hysteretic sub-kT switching in hardware; however, remnant polarization (Pr) is small and so only part of the off-state is in the NC regime. The work presented herein will describe the importance of treating NCFETs as a complementary pair and how this can be leveraged to break the perceived mutual exclusivity between super-steep and nonhysteretic switching when both the on-and off-states are in the NC regime, through an effect described as complementary capacitance matching (CCM).…”