Junction Design and Complementary Capacitance Matching for NCFET CMOS Logic

Abstract

Negative capacitance field effect transistors (NCFETs) are modeled in this study, with an emphasis on junction design, implications of complementary logic, and device Vt menu enablement. Contrary to conventional MOSFET design, increased junction overlap is beneficial to NCFETs, provided the remnant polarization (Pr) is high enough. Combining broad junctions with complementary capacitance matching (CCM) in MFMIS (metal/ferroelectric/metal/insulator/semiconductor) NCFETs, it is shown that super-steep and non-hysteretic switching are not mutually exclusive, and that it is theoretically possible to achieve non-hysteretic sub-5 mV/dec SS over > 6 decades. In a CMOS circuit, due to CCM, low-Vt pairs provide steeper subthreshold swing (SS) than high-Vt pairs. Transient power/performance is also modeled, and it is shown that a DCoptimal NCFET design, employing broad junctions, CCM, and a low-Vt NFET/PFET pair, does not translate to improved AC power/performance in unloaded circuits compared to a conventional FET reference. It is also shown that the same nonhysteretic DC design point is hysteretic in AC and may also lead to full polarization switching at higher voltages. Thus, a usable voltage window for AC NCFET operation forces a retreat from the DC-optimal design point.

5 nm Ultrathin Crystalline Ferroelectric P(VDF‐TrFE)‐Brush Tuned for Hysteresis‐Free Sub 60 mV dec−1 Negative‐Capacitance Transistors

“…Recently, researchers have found that the proper capacitance matching between DE and FE layers can ensure the hysteresis-free device operation. [7,[23][24][25] However, the FE/DE capacitance matching is only feasible via a precise thickness control of FE and DE layers, which is often very difficult to achieve. Therefore, even with significant engineering efforts, the realization of hysteresis-free NC-FET with reduced SS has been challenging.…”