2012
DOI: 10.1109/tdmr.2011.2163408
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Bias-Stress-Induced Instability of Polymer Thin-Film Transistor Based on Poly(3-Hexylthiophene)

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Cited by 15 publications
(4 citation statements)
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“…A PBS, on the other hand, tended to reset VT to its pristine value only for TFTs on Si. This is related to the movement of holes and, consequently, traps being filled or emptied at the semiconductor/dielectric interface under the presence of a constant gate voltage [25,45]. Liu et al showed that holes, which are induced in the channel during the prolonged application of a negative bias stress, are trapped in defect states located at the semiconductor interface with SiO2.…”
Section: B Current Versus Voltage Shifts Under Stressmentioning
confidence: 99%
“…A PBS, on the other hand, tended to reset VT to its pristine value only for TFTs on Si. This is related to the movement of holes and, consequently, traps being filled or emptied at the semiconductor/dielectric interface under the presence of a constant gate voltage [25,45]. Liu et al showed that holes, which are induced in the channel during the prolonged application of a negative bias stress, are trapped in defect states located at the semiconductor interface with SiO2.…”
Section: B Current Versus Voltage Shifts Under Stressmentioning
confidence: 99%
“…Quantitative analysis for the instability, however, has been rarely reported while there have been a lot of works for high mobility PTFTs. Although previous studies for bias stress instability analyzed the positive charge (hole) trapping into gate insulator or its interface as the main origin of stressinduced instability [4], [5], the quantitative investigation and analysis for its correlated factors is the urgent research that should be performed in advance since the physical origins of the bias stress-induced instability strongly interact in the actual polymer semiconductor devices.…”
Section: Introductionmentioning
confidence: 99%
“…It is well known that P3HT based OTFTs show a decrease of current until a plateau is reached, 30 as determined by charge trapping inside deep energy states of P3HT. 31 We measured the drain current as a function of time, for a 10% blend of AuNP-BPT coated devices, by applying a constant bias-stress at the drain V d ¼ À5 V and a gate voltage V g calculated from the threshold voltage of the device extracted from the saturation regime with V g À V th ¼ À5 V for a time of 30 minutes. The drain current decreases in the rst few minutes and reaches a plateau at different times depending on the sample (see Fig.…”
mentioning
confidence: 99%