Bidirectional interconnect design for low latency high bandwidth NoC

Kumar, Reeshav; Deshpande, Hrishikesh; Choi, Gwan; Sprintson, Alex; Gratz, Paul V.

doi:10.1109/icicdt.2013.6563340

Cited by 2 publications

References 4 publications

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An efficient network on-chip architecture based on isolating local and non-local communications

Akhlaghi

Kamal

Afzali-Kusha

et al. 2015

Computers & Electrical Engineering

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In this paper, we propose a scheme for reducing the latency of packets transmitted via on-chip interconnect network in MultiProcessor Systems on Chips (MPSoCs). In this scheme, the network architecture separates the packets transmitted to near destinations from those transmitted to distant ones by using two network layers. These two layers are realized by dividing the channel width among the cores. The optimum ratio for the channel width division is a function of relative significances of the two types of communications. Simulation results indicate that for non-uniform traffic constituting of more than 30 percent local traffic, the proposed network, on average provides 64% and 70% improvement over the conventional one in terms of average network latency and Energy-Delay product (EDP), respectively. Also, for uniform and NED traffic patterns, by adjusting the number of hops between local nodes to include approximately 55 percent of total communications in local ones, the proposed architecture provides the latency reduction of 50%.

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An efficient network on-chip architecture based on isolating local and non-local communications

Akhlaghi

Kamal

Afzali-Kusha

et al. 2015

Computers & Electrical Engineering

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Effects of the NoC architecture in the performance of NoC-based MPSoCs

Silva

Oliveira

Moraes

2014

2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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The goal of this work is to evaluate the impact of multiple Network-on-Chip (NoC) architectural parameters over the performance of applications running on Multiprocessors Systems-on-Chip (MPSoCs) using message passing as communication protocol. Nowadays, MPSoCs have so many constraints of performance that bus-based communications are not able to achieve the full potential of MPSoCs, therefore, the adoption of NoCs is a trend for the communication infrastructure in MPSoCs due to their performance compared to bus-based architectures and scalability compared to crossbar-based architectures. However, there is an important gap in the literature with works evaluating the impact of NoC parameters in the performance of applications running in MPSoCs. This work proposes the evaluation of how different NoC parameters affect applications running in a real MPSoC, trying to answer the following question: how does a given NoC parameter affect the performance of the MPSoC?

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Bidirectional interconnect design for low latency high bandwidth NoC

Cited by 2 publications

References 4 publications

An efficient network on-chip architecture based on isolating local and non-local communications

An efficient network on-chip architecture based on isolating local and non-local communications

Effects of the NoC architecture in the performance of NoC-based MPSoCs

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