BiLink: A high performance NoC router architecture using bi-directional link with double data rate

Zhu, Jingyang; Qian, Zhiliang; Tsui, Chi-Ying

doi:10.1016/j.vlsi.2016.02.006

Cited by 7 publications

(6 citation statements)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In conventional OR structures, two ports communicate via a pair of single-directional waveguides, one for transmitting (TX) data and another for receiving (RX) data; however, NoC-based OR architectures cofigured with bidirectional channels, which can offer signficant performance advantages over conventional NoC-based ORs equipped with unidirectional channels, have been proposed [21,22]. Thus, in this section, we use bidirectional waveguides to replace original single-directional waveguides within the OR.…”

Section: Design Of Extended or Structurementioning

confidence: 99%

Designs of low insertion loss optical router and reliable routing for 3D optical network-on-chip

Guo

2016

Sci. China Inf. Sci.

View full text Add to dashboard Cite

Three-Dimensional Optical Network-on-Chip (3D ONoC) has recently emerged as a high-performance on-chip communication solution; however, owing to the intrinsic characteristics of photonic devices in existing 3D ONoC, the insertion loss caused by undesirable coupling among optical signals degrades network performance. Considering manufacturing defects and unpredictable noise sources that cause the failure of Optical Routers (ORs) in 3D ONoC, previous work simply abandoned the disabled OR when computing the restore path. In this paper, we propose a new OR structure that reduces insertion loss, and we present the design of a novel adaptive routing algorithm, FTRA-BL, based on the new OR structure with bidirectional waveguides, without abandoning any disabled ORs. Our FTRA-BL selects the normal waveguide in the disabled OR as the backup link so that the best macroscopic restore path can be guaranteed. Simulation results show that our method performs better than previous work in improving transmission reliability and latency.

show abstract

Section: Design Of Extended or Structurementioning

confidence: 99%

Designs of low insertion loss optical router and reliable routing for 3D optical network-on-chip

Guo

2016

Sci. China Inf. Sci.

View full text Add to dashboard Cite

show abstract

“…Because of the extension of systems of many-core in novel applications such as machine learning, artificial intelligence and big data, the NoC R has to carry over a huge amount of connection data between processors. For instance, the Google Brain project uses about 1,000 machines to instruct a profound nervous network (Zhu et al, 2016). NoC can improve the bandwidth scalability, energy efficiency, reliability and reusability in compared to traditional bus-based architectures (Daki et al, 2017;Sethi et al, 2017).…”

Section: Introductionmentioning

confidence: 99%

Tasks mapping in the network on a chip using an improved optimization algorithm

Darbandi¹,

Ramtin

Sharafi

2020

IJPCC

View full text Add to dashboard Cite

Purpose A set of routers that are connected over communication channels can from network-on-chip (NoC). High performance, scalability, modularity and the ability to parallel the structure of the communications are some of its advantages. Because of the growing number of cores of NoC, their arrangement has got more valuable. The mapping action is done based on assigning different functional units to different nodes on the NoC, and the way it is done contains a significant effect on implementation and network power utilization. The NoC mapping issue is one of the NP-hard problems. Therefore, for achieving optimal or near-optimal answers, meta-heuristic algorithms are the perfect choices. The purpose of this paper is to design a novel procedure for mapping process cores for reducing communication delays and cost parameters. A multi-objective particle swarm optimization algorithm standing on crowding distance (MOPSO-CD) has been used for this purpose. Design/methodology/approach In the proposed approach, in which the two-dimensional mesh topology has been used as base construction, the mapping operation is divided into two stages as follows: allocating the tasks to suitable cores of intellectual property; and plotting the map of these cores in a specific tile on the platform of NoC. Findings The proposed method has dramatically improved the related problems and limitations of meta-heuristic algorithms. This algorithm performs better than the particle swarm optimization (PSO) and genetic algorithm in convergence to the Pareto, producing a proficiently divided collection of solving ways and the computational time. The results of the simulation also show that the delay parameter of the proposed method is 1.1 per cent better than the genetic algorithm and 0.5 per cent better than the PSO algorithm. Also, in the communication cost parameter, the proposed method has 2.7 per cent better action than a genetic algorithm and 0.16 per cent better action than the PSO algorithm. Originality/value As yet, the MOPSO-CD algorithm has not been used for solving the task mapping issue in the NoC.

show abstract

“…In a BiNoC [63], a dynamic reconfigurable architecture has been suggested to change of the path of the links in the runtime traffic situation. To accommodate uneven distributed traffic in the core of the network, BiNoC architecture was initially introduced and further optimized in FSNoC [64] and BiLink [65]. Main difference between these architectures and 2X-Link is how the link direction control is implemented.…”

Section: Bi-noc Router Architecturementioning

confidence: 99%

“…Dynamic reconfigurable router architectures have been suggested to enhance NoC proficiency by changing the path of the links in the runtime traffic situation, since normal traffic pattern is commonly unevenly distributed in the core of the network. To accommodate for such kind of traffic pattern, a bi-directional NoC ((BiNoC) [63] architecture was presented and further optimized as FSNoC [64] and BiLink [65]. However, the greater part of the accentuation on the current reconfigurable NoC architecture has been concentrating on upgrading the design of the switch itself.…”

Section: Bi-noc Router Architecturementioning

confidence: 99%

“…Over a single physical channel, an extra coding unit was inserted between each pair of routers to enable the data transmission from both ends at a time. BiLink [65] uses an additional link stage amongst routers and transmits two flits in one link for every clock cycle using stage pipelining if both routers require utilizing the current link. To increase additional effective bandwidth, each link path can be arranged in every clock cycle to supply different traffic loads from both sides.…”

Section: Bi-noc Router Architecturementioning

confidence: 99%

See 1 more Smart Citation

Contribution to the architecture and implementation of Bi-NoC routers for multi-synchronous GALS systems

Kamal

View full text Add to dashboard Cite

Networks-on-Chip (NoC) is an emerging on-chip interconnection centric platform that influences the modern high speed communication infrastructure to improve on-chip communication challenges in the recent many core System-on-Chip (SoC) designs. Continuing shrinkage of feature dimensions of Nano-scale semiconductor devices has been raised serious concerns of the reliability, signal integrity, and quality of services (QoS) of traditional bus based on-chip interconnect infrastructure. NoC represents a major standard move to address these concerns by incorporating state-of-the-art of high-speed data network components (such as routers and switches) and packet-based routing protocols in novel on-chip network infrastructure. A NoC¿s aim is to provide a reliable on-chip communication platform to facilitate scalable gigascale SoC design. A multi-synchronous bi-directional NoC's router architecture is proposed in this thesis to enhance the performance of available on-chip communication platform. Using parameterized RTL implementation, we first divide microarchitecture into six blocks as multi-synchronous FIFO, Arbiters, Route Computation, Switch Allocator, Virtual channel Allocator, and Network Interface. Overall architecture of the proposed NoC router consists of five bi-directional ports which supports data transfer between two clock domain of completely arbitrary phase and frequency; and best suited for the Distributed Scalable Predictable Interconnect Networks (DSPIN). In this router, each communication channel allows itself to be dynamically reconfigured to transmit flits in either direction. This added flexibility promises better bandwidth utilization, lower packet delivery latency, and higher packet consumption rate. We first evaluated performances of each blocks in terms of power, area, and delay with optimizes these blocks to satisfy network key parameters, as well as the impact of allocation on overall network performance. Using structural modeling style and parametric Verilog HDL, all blocks are individually implemented, tested and verified. Finally, all individual blocks are combined to implement bi-directional router¿s architecture as a whole. Here, we vary the number of nodes for performance evaluation. A multi-synchronous bi-directional router microarchitecture have been implemented in this thesis, is sufficient to provide throughput challenges, interconnect issues, low latency and high bandwidth in the future Globally Asynchronous Locally Synchronous Systems (GALS) system. In concise, to enhance the performance of on-chip communications of GALS Systems, a dynamic reconfigurable multi-synchronous router architecture is proposed and implemented to increase the NoC efficiency with changing the path of the communication link in the runtime traffic situation. In order to address GALS issues and bandwidth requirements, the proposed multi-synchronous bidirectional NoC¿s router is developed and it gives reliable higher packet consumption rate, better bandwidth utilization with lower packet delivery latency. All the input/output ports of the proposed router behave as a bi-directional ports and communicate through a novel multi-synchronous first-in first-out (FIFO) buffer. The bidirectional port is controlled by a dynamic channel control module which provides a dynamic reconfigurable channel to the router itself and associated with sub-modules. This proposed multi-synchronous bidirectional router architecture is synthesized using Xilinx ISE 14.7 and FPGA Virtex 6 family device XC6VLX760 is considered as target technology. The performance of the proposed architecture is evaluated in terms of power, area, and delay. Las redes en chip (NoC) constituyen una plataforma de interconexión en chip emergente que influye en la moderna infraestructura de comunicación de alta velocidad para mejorar los desafíos de comunicación en chip de los recientes diseños de sistemas en chip (SoC). La continua reducción de las dimensiones de los dispositivos semiconductores a escala nanométrica ha planteado serias preocupaciones en cuanto a la fiabilidad, la integridad de la señal y la calidad de los servicios (QoS) de la infraestructura de interconexión en chip basada en canal tradicional. NoC representa un paso estándar importante para abordar estas cuestiones incorporando tecnología moderna de componentes de red de datos de alta velocidad (como enrutadores y conmutadores) y protocolos de enrutamiento basados en paquetes en la nueva infraestructura de red en chip. El objetivo de NoC es proporcionar una plataforma de comunicación en chip fiable para facilitar el diseño escalable de SoC. En esta tesis se propone una arquitectura de enrutador NoC bidireccional multi-síncrono para mejorar el rendimiento de la plataforma de comunicación en chip disponible. Utilizando una implementación RTL parametrizada, primero dividimos la microarquitectura en seis bloques como FIFO multi-síncrono, arbitradores, Cálculo de Rutas, Asignador de Conmutadores, Asignador de canales virtuales e Interfaz de Red. La arquitectura general del enrutador NoC propuesto consta de cinco puertos bidireccionales que soportan la transferencia de datos entre dos dominios de reloj de fase y frecuencia completamente arbitrarias; además, se muestra más adecuada para las Redes de Interconexión Predecibles Escalables y Distribuidas (DSPIN). En este enrutador, cada canal de comunicación permite ser reconfigurado dinámicamente para transmitir las unidades de control de flujo en cualquier dirección. Esta flexibilidad añadida promete una mejor utilización del ancho de banda, una menor latencia de entrega de paquetes y una mayor tasa de consumo de paquetes. Primero evaluamos las prestaciones de cada bloque en términos de potencia, área y retraso, optimizando estos bloques para satisfacer los parámetros clave de la red, así como el impacto de la asignación en el rendimiento general de la red. Utilizando el estilo de modelado estructural y el Verilog HDL paramétrico, todos los bloques se implementan, prueban y verifican individualmente. Finalmente, todos los bloques individuales se combinan para implementar la arquitectura de enrutador bidireccional como un todo. Aquí, variamos el número de nodos para la evaluación del rendimiento. En forma concisa, para mejorar el rendimiento de las comunicaciones en chip de los sistemas GALS, se propone e implementa una arquitectura de enrutador multi-síncrono reconfigurable dinámico para aumentar la eficiencia de NoC con el cambio de la ruta del enlace de comunicación en la situación de tráfico en tiempo de ejecución. Con el fin de abordar los problemas de GALS y los requisitos de la banda ancha, el enrutador de NoC bidireccional multi-síncrono propuesto se desarrolla y proporciona una mayor tasa de consumo de paquetes, una mejor utilización de la banda ancha con menor latencia de entrega de paquetes. Todos los puertos de entrada / salida del enrutador propuesto se comportan como puertos bidireccionales y se comunican a través de un nuevo búfer multi-síncrono de tipo FIFO (primera entrada primera salida). El puerto bidireccional es controlado por un módulo de control de canal dinámico que proporciona un canal reconfigurable dinámico al propio enrutador y asociado con sub-módulos. Esta propuesta arquitectura de enrutador bidireccional multi-síncrono se sintetiza utilizando Xilinx ISE 14.7 y el dispositivo FPGA Virtex 6 XC6VLX760 se considera como la tecnología objetivo. El rendimiento de la arquitectura propuesta se evalúa en términos de potencia, área y retraso.

show abstract

BiLink: A high performance NoC router architecture using bi-directional link with double data rate

Cited by 7 publications

References 21 publications

Designs of low insertion loss optical router and reliable routing for 3D optical network-on-chip

Designs of low insertion loss optical router and reliable routing for 3D optical network-on-chip

Tasks mapping in the network on a chip using an improved optimization algorithm

Contribution to the architecture and implementation of Bi-NoC routers for multi-synchronous GALS systems

Contact Info

Product

Resources

About