Binary Multiplication Using Hybrid MOS and Multi-Gate Single-Electron Transistors

Deng, Guoqing; Chen, Chunhong

doi:10.1109/tvlsi.2012.2217993

Cited by 18 publications

(4 citation statements)

References 23 publications

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“…[6][7][8]. Among these new technologies, CNFETs have attracted a lot of attention as a potential successor for CMOS because of its outstanding characteristics such as similarities with MOSFET, high carrier mobility, high ION/IOFF ratio, unique one dimensional band structure and near ballistic transportation [9,10].…”

Section: Introductionmentioning

confidence: 99%

Energy Efficient Tri-State CNFET Ternary Logic Gates

Tabrizchi¹,

Sharifi²,

Badawy³

2018

Preprint

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Traditional silicon binary circuits continue to face challenges such as high leakage power dissipation and large area of interconnections. Multiple-Valued Logic (MVL) and nano-devices are two feasible solutions to overcome these problems. In this paper, we present a novel method to design ternary logic circuits based on Carbon Nanotube Field Effect Transistors (CNFETs). The proposed designs use the unique properties of CNFETs, e.g., adjusting the Carbon Nanotube (CNT) diameters to have the desired threshold voltage and have the same mobility of P-FET and N-FET transistors. Each of our designed logic circuits implements a logic function and its complementary via a control signal. Also, these circuits have a high impedance state which saves power while the circuits are not in use. We show a more detailed application of our approach by designing a two-digit adder-subtractor circuit. We simulate the proposed ternary circuits using HSPICE via standard 32nm CNFET technology. The simulation results indicate the correct operation of the designs under different process, voltage and temperature (PVT) variations. Moreover, we designed a two-digit adder/subtractor and a power efficient ternary logic ALU based on the proposed gates. Simulation results show that the two-digit adder/subtractor using our proposed gates has 12X and 5X lower power consumption and PDP (power delay product) respectively, compared to previous designs.

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Section: Introductionmentioning

confidence: 99%

Energy Efficient Tri-State CNFET Ternary Logic Gates

Tabrizchi¹,

Sharifi²,

Badawy³

2018

Preprint

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show abstract

“…Counters are much faster than conventional adders because they could act without carry signal along their digital stages. Counters are the basic blocks, which are used to acquire the partial products in the multiplication process (Deng & Chen, 2013). Thus, improving the power performance of these structures could lead to remarkable saving of the power used by the entire multiplier.…”

Section: Introductionmentioning

confidence: 99%

Digital counter cell design using carbon nanotube FETs

Bagherizadeh

Moaiyeri

Eshghi

2017

Journal of Applied Research and Technology

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Compressor and counter cells are the basic blocks used to accumulate the partial products in a multiplication process. In this paper, novel high speed and low power carbon nanotube counter cells are suggested. The efficiency of circuits is improved by using carbon nanotube field-effect transistors (CNFETs). The proposed designs are 4-to-3, 5-to-3, 6-to-3, and 7-to-3 counters. Using HSPICE, these proposed designs are simulated at different conditions. Simulation results confirm that the proposed designs are the fastest counters with lowest PDP in different working circumstance.

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“…[1][2][3][4] Apart from a well-accepted simulator (SIMON), there are a few models of single electron transistor (SET) which have been used extensively by the researcher for simulating single electronics circuits. [10][11][12][13][14] So the switching speed or more specifically the delay analysis of these devices needs to be studied extensively for proper designing of practical integrated circuits. [10][11][12][13][14] So the switching speed or more specifically the delay analysis of these devices needs to be studied extensively for proper designing of practical integrated circuits.…”

Section: Introductionmentioning

confidence: 99%

“…[5][6][7][8][9] Due to the lower gain of single electronics devices compared with its CMOS counterpart, they are mostly used in the circuits designed targeting digital applications. [10][11][12][13][14] So the switching speed or more specifically the delay analysis of these devices needs to be studied extensively for proper designing of practical integrated circuits. The signal processing in single electronics devices is stochastic in nature which involves random processes in delay analysis of these devices.…”

Section: Introductionmentioning

confidence: 99%

Error probability independent delay analysis of single electronics circuits

Jain

Ghosh²,

Dutta

et al. 2017

Circuit Theory & Apps

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This study based on Poisson process and orthodox theory of single electron tunneling for the first time proposes an error probability independent delay model for delay calculation of single electronics circuits, involving multiple tunneling events. The Poisson process assumes that the tunneling events are independent of each other, but in real single electronics circuits they are correlated through space and time, so this effect has been considered and included in the proposed model. The dependence of tunneling rates on the logic transition is thoroughly investigated. Finally, the model is applied to different logic gates, and the result is compared with the well known Monte Carlo approach to prove the accuracy of the proposed model.

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Binary Multiplication Using Hybrid MOS and Multi-Gate Single-Electron Transistors

Cited by 18 publications

References 23 publications

Energy Efficient Tri-State CNFET Ternary Logic Gates

Energy Efficient Tri-State CNFET Ternary Logic Gates

Digital counter cell design using carbon nanotube FETs

Error probability independent delay analysis of single electronics circuits

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