Binary SOVA and Nonbinary LDPC Codes for Turbo Equalization in Magnetic Recording Channels

Jeon, Seungjune; Kumar, B. V. K. Vijaya

doi:10.1109/tmag.2010.2043068

Cited by 19 publications

(9 citation statements)

References 13 publications

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“…In the iterative decoding process assume that the soft output Viterbi algorithm (SOVA) [19] is used as the PR channel detector and the Qary sum-product algorithm (QSPA) is employed as non-binary LDPC decoders [20]. The technique for conversion between a symbols reliability in LDPC decoder and q-bits reliability in SOVA is present in [21]. The signal to noise ratio (in dB) of the partial response channel is defined as…”

Section: Channel Modelmentioning

confidence: 99%

A high rate non-binary QC-LDPC codes in high order Galois Field for PR2 and EPR2 channels

Kupimai

2014

2014 11th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technolo

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In this paper, the new structure of high rate nonbinary QC-LDPC codes based on the circulant permutation matrices is proposed. The construction of parity-check matrix of the proposed codes is obtained from (2, L) regular QC-LDPC codes. The parity-check matrix of the proposed codes has girth greater than 8. Simulation results over PR channels with the high order Galois Field show that the bit error rate and the symbol error rate performance of the proposed codes is better than those of the random non-binary LDPC codes, both in PR2 channel and EPR2 channel.

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Section: Channel Modelmentioning

confidence: 99%

A high rate non-binary QC-LDPC codes in high order Galois Field for PR2 and EPR2 channels

Kupimai

2014

2014 11th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technolo

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“…Another interesting point of the proposed algorithm is that it does not require actual marginalization by summing many joint bit probabilities (or symbol probabilities) terms when we obtain the marginal probability for a bit from those multiple-bit symbol probabilities. The proposed algorithm was published in [45,48].…”

Section: Thesis Contributionsmentioning

confidence: 99%

Low-Density Parity Check Codes

Wu¹

2009

Contemporary Coding Techniques and Applications for Mobile Communications

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For high density magnetic recording channels and memory systems, low-density parity-check (LDPC) codes with probabilistic decoding are replacing Reed-Solomon (RS) codes or Bose-Chaudhuri-Hocquenghem (BCH) codes with conventional algebraic decoding. The main benefit of LDPC codes over the RS and BCH codes is that LDPC codes can provide lower error probabilities than equivalent conventional codes if the conditions of magnetic recording channels or memory systems are the same. In other words, in order to achieve the same error probabilities, LDPC codes can tolerate lower signal-to-noise-ratio conditions than the conventional codes, which can imply higher densities and lower media costs. These advantages of LDPC codes are possible at the cost of the increased decoder complexity over the conventional decoding.The main themes of this thesis are (1) to determine probabilistic input to the LDPC decoders from the channel detectors in magnetic recording channels or memory systems with low complexity and (2) AcknowledgmentsI would like to thank Prof. Kumar for providing me with a unique opportunity and an ideal environment to study signal processing and error correcting codes for data storage and memory systems. I respect his patience and believing in students. I was very lucky and I will miss the time I stayed here.I would like to thank Prof. Bain, Prof. Li, and Dr. Cheng for reading my thesis during their busiest time and providing many suggestions and very detailed feedback.I would also like to thank Dr. Cheng for bringing my interest into the fascinating problem of protecting memory systems on spacecraft and for his very detailed comments on the manuscripts of the papers on this topic.

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“…T HE max * operation [1] is the computational kernel of the logarithmic maximum a posteriori (Log-MAP) algorithm employed in the decoding of turbo and low-density paritycheck codes. These codes have become a reference for several applications, such as magnetic disk reliability and telemetry [2], [3]. For this reason, several research efforts have been devoted to reduce the complexity of the max * operation both at algorithmic and implementation level, to obtain lowcomplexity very large scale integration architectures [4]- [10].…”

Section: Introductionmentioning

confidence: 99%

“…Even if low-complexity algorithms for the computation of the two-input max * operation lead to these previously published efficient architectures, in this paper it is shown that further hardware complexity can be saved by analyzing the n-input max * operation as a whole. Specifically, this paper is motivated by [12], where it was shown that by exploiting the Chebyshev inequality the n-input max * operation can be approximated as max * {X } ≈ y 1 + log[(1 + K 1 exp{−δ})] + K 2 (2) where X = {x 1 , . .…”

Section: Introductionmentioning

confidence: 99%

“…Furthermore, in [14], it has been shown that both the Log-MAP approximation of (2) and the constant Log-MAP algorithm [4] achieve nearly an optimal bit error rate (BER) performance. However, the Log-MAP architecture presented in [14] for approximating (2) was more complex than n − 1 instances of the constant Log-MAP architecture [4]. Thus, the efficient hardware implementation of (2) leading to a very low-complexity turbo decoding architecture is still an open problem.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Simplified Log-MAP Algorithm for Very Low-Complexity Turbo Decoder Hardware Architectures

Martina

Papaharalabos

Mathiopoulos

et al. 2014

IEEE Trans. Instrum. Meas.

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Motivated by the importance of hardware implementation in practical turbo decoders, a simplified, yet effective, n-input max * approximation algorithm is proposed with the aim being its efficient implementation for very low-complexity turbo decoder hardware architectures. The simplification is obtained using an appropriate digital circuit for finding the first two maximum values in a set of n data that embeds the computation of a correction term. Various implementation results show that the proposed architecture is simpler by 30%, on average, than the constant logarithmic-maximum a posteriori (Log-MAP) one, in terms of chip area with the same delay. This comes at the expense of very small performance degradation, in the order of 0.1 dB for up to moderate bit error rates, e.g., 10 −5 , assuming binary turbo codes. However, when applying scaling to the extrinsic information, the proposed algorithm achieves almost identical Log-MAP turbo code performance for both binary and double-binary turbo codes, without increasing noticeably the implementation complexity.Index Terms-Digital circuit, logarithmic maximum a posteriori (Log-MAP), Max-Log-MAP, turbo codes. (SM'07) received the Dr.Eng. degree (summa cum laude) and the Ph.D. degree in electrical engineering from Politecnico di Torino, Torino, Italy, in 1986 and 1992, respectively. He was with Centro Studi e Laboratori in Telecomunicazioni, Torino, from 1986 to 1988, as a Researcher, involved in the standardization activities for the GSM system. Since 1992, he has been an Assistant Professor and then Associate Professor with the Electronic Department, where he is a member of the VLSI-Laboratory Group. In the frame of National and European research projects, he was a co-designer of several ASIC and FPGA implementations in the fields of artificial intelligence, computer networks, digital signal processing, and transmission and coding. He has co-authored more than 160 journal and conference papers in the areas of ASIC-SoC development, architectural synthesis, and VLSI circuit modeling and optimization. His current research interests include several aspects of the design of digital integrated circuits and systems, with special emphasis on high-performance architecture development (especially for wireless communications and multimedia applications) and on-chip interconnect modeling and optimization.

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Binary SOVA and Nonbinary LDPC Codes for Turbo Equalization in Magnetic Recording Channels

Cited by 19 publications

References 13 publications

A high rate non-binary QC-LDPC codes in high order Galois Field for PR2 and EPR2 channels

A high rate non-binary QC-LDPC codes in high order Galois Field for PR2 and EPR2 channels

Low-Density Parity Check Codes

Simplified Log-MAP Algorithm for Very Low-Complexity Turbo Decoder Hardware Architectures

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