Simplified Log-MAP Algorithm for Very Low-Complexity Turbo Decoder Hardware Architectures

Abstract

Motivated by the importance of hardware implementation in practical turbo decoders, a simplified, yet effective, n-input max * approximation algorithm is proposed with the aim being its efficient implementation for very low-complexity turbo decoder hardware architectures. The simplification is obtained using an appropriate digital circuit for finding the first two maximum values in a set of n data that embeds the computation of a correction term. Various implementation results show that the proposed architecture is simpler by 30%, on average, than the constant logarithmic-maximum a posteriori (Log-MAP) one, in terms of chip area with the same delay. This comes at the expense of very small performance degradation, in the order of 0.1 dB for up to moderate bit error rates, e.g., 10 −5 , assuming binary turbo codes. However, when applying scaling to the extrinsic information, the proposed algorithm achieves almost identical Log-MAP turbo code performance for both binary and double-binary turbo codes, without increasing noticeably the implementation complexity.Index Terms-Digital circuit, logarithmic maximum a posteriori (Log-MAP), Max-Log-MAP, turbo codes. (SM'07) received the Dr.Eng. degree (summa cum laude) and the Ph.D. degree in electrical engineering from Politecnico di Torino, Torino, Italy, in 1986 and 1992, respectively. He was with Centro Studi e Laboratori in Telecomunicazioni, Torino, from 1986 to 1988, as a Researcher, involved in the standardization activities for the GSM system. Since 1992, he has been an Assistant Professor and then Associate Professor with the Electronic Department, where he is a member of the VLSI-Laboratory Group. In the frame of National and European research projects, he was a co-designer of several ASIC and FPGA implementations in the fields of artificial intelligence, computer networks, digital signal processing, and transmission and coding. He has co-authored more than 160 journal and conference papers in the areas of ASIC-SoC development, architectural synthesis, and VLSI circuit modeling and optimization. His current research interests include several aspects of the design of digital integrated circuits and systems, with special emphasis on high-performance architecture development (especially for wireless communications and multimedia applications) and on-chip interconnect modeling and optimization.

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