Bio‐inspired network on chip having both guaranteed throughput and best effort services using fault‐tolerant algorithm

Abstract

Network-on-chip (NoC) is a communication framework for multiple cores connected together in a system-on-chip (SoC). Different NoC architectures have provided quality of service (QoS) parameters of best effort (BE) and guaranteed throughput (GT). GT services are provided by having a dedicated connection using circuit switching or connection-oriented mechanism of packet switching. GT traffic is usually preferred for real-time traffic such as video processing and multimedia applications. BE services are provided using packet switching. Cache updates is an example of BE noncritical traffic. In this paper, we implement a novel biologically inspired fault-tolerant algorithm that provides both GT and BE QoS. In order to provide fault tolerance, the router architectures is also updated. The bio-inspired, fault-tolerant techniques are a novel way to provide fault tolerance in NoC. Faults in the NoC arise as the size of the devices are shrinking on the NoC, which include the router, links, and processing elements (PEs), to accommodate the complex communication requirements of applications. The proposed NoC's fault-tolerant methods (synaptogenesis and sprouting) are adapted from the biological brain's robust fault-tolerant mechanisms. From the experimental results, the throughput and bandwidth utilization are dropped by 3.55 and 4.87%, respectively, during the recovery from faults. The interflit arrival time and packet network latency are increased by only 7.03 and 22.60%, respectively, during the recovery from faults. The algorithm also performs as efficiently as the traditional fault-tolerant techniques.

Bio-Inspired Solutions and Its Impact on Real-World Problems: A Network on Chip (NoC) Perspective

“…The flits are saved in best effort queue (BQ) or guaranteed throughput queue (GQ) depending on the source of the flit. Round-robin slot mechanism is used in BE + GT services, whereas GT flits have the highest priority compared to BE flits [19,20]. The port architecture for BE + GT is shown in Figure 7.…”

Implementation of NoC on FPGA with Area and Power Optimization

“…Keeping in view the architecture of a port, crossbar connection is made. A port also has separate paths for incoming and outgoing data; in a crossbar connection of a port with another, input paths of each port is connected with output paths of every other port [4,5]. In a 2x2 NoC, all routers are edge routers so for optimizing the area and power utilization we skipped the unused ports for edge routers.…”