BIST‐Based Fault Diagnosis in the Presence of Embedded Memories

Savir, J.

doi:10.1155/2001/32515

Cited by 2 publications

(1 citation statement)

References 9 publications

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“…Work related to diagnosis of faults in circuits surrounding embedded memories was recently reported in [12,14,16]. Here also, no connections were allowed between the Prelogic and the Postlogic.…”

Section: Introductionmentioning

confidence: 99%

BIST Analysis of an Embedded Memory Associated Logic

Savir

2000

VLSI Design

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Of late some interesting and useful work has been done on the problem of testing logic surrounding embedded memories. This work assumes that the logic surrounding the memory is functionally partitioned and that the different partitions are logically isolated one from the other.This paper expands upon past work using a more flexible design rule which allows feed-forward connections between the data-path Prelogic and Postlogic. The connections are such that there is no feedback from the memory outputs to its inputs, and both the Prelogic and the Postlogic are disconnected from the Address and Control logic. Under this design rule we show the auxiliary circuits used to determine the random pattern testability of faults in the circuitry driving the address inputs and the controls of the two-port memory.The techniques described herein are intended to be used in conjunction with the cutting algorithm for testability measurement in built-in self-test (BIST) designs [2, 11, 17], but may also be suitable for use with other detection probability tools [9, 19], and simulation tools [20].

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Section: Introductionmentioning

confidence: 99%