Exploiting an Infrastructure IP to Reduce the Costs of Memory Diagnosis Costs in SoCs

Bernardi, P.; Grosso, M.; Rebaudengo, Maurizio; Reorda, M. Sonza

doi:10.1109/ets.2005.23

Cited by 3 publications

(3 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…An IEEE 1500 wrapper is included in the BIST design to interface the processor with the outside, supporting the commands for running the BIST and accessing to its results. The wrapper is compliant with the suggestions of the 1500 standard and allows the execution of the diagnostic procedures by means of an access protocol common to all the other memory BISTs included in the SoC structure [26].…”

Section: Experimental Set-upmentioning

confidence: 99%

Embedded Memory Diagnosis: An Industrial Workflow

Appello

Tancorre

Bernardi

et al. 2006

2006 IEEE International Test Conference

View full text Add to dashboard Cite

Embedded memory modules are sensitive components that deeply influence production yield of integrated devices. For fast yield improvement, an efficient manufacturing test must supply advanced defect characterization that helps in discovering technology weaknesses and finding strategies for improvement. This paper presents an industrial workflow for embedded memory diagnosis. It is based on the integration of March-based diagnostic BIST hardware in an IEEE 1500-compliant environment, and on a novel diagnostic algorithm for determining the fault model associated to the retrieved syndromes. An experimental implementation showing the feasibility of the approach is presented.

show abstract

Section: Experimental Set-upmentioning

confidence: 99%

Embedded Memory Diagnosis: An Industrial Workflow

Appello

Tancorre

Bernardi

et al. 2006

2006 IEEE International Test Conference

View full text Add to dashboard Cite

show abstract

“…In that case, the authors of [5] suggested the inclusion of an Infrastructure IP (I-IP) in charge of properly managing the activation of the test algorithms by the different cores, retrieving the corresponding results, and automatically implementing the steps required by the diagnosis process. This solution may provide some benefits, e.g., in terms of flexibility, ATE requirements, and test time, with a reduced cost in terms of extra hardware.…”

Section: Introductionmentioning

confidence: 99%

A New Architecture to Cross-Fertilize On-Line and Manufacturing Testing

Bernardi

Reorda

2011

2011 Asian Test Symposium

Self Cite

View full text Add to dashboard Cite

1 -This paper deals with the on-line test of SoCs including cores equipped with BIST circuitry and IEEE 1500 wrappers. A method is proposed, which exploits an Infrastructure IP named OTC to manage the on-line test; the OTC module activates the test and provides the related results under the software control of the CPU, thus allowing the SoC to autonomously and flexibly support the on-line test, both at startup and during the normal operation phase. The main advantage of the proposed method lies in the fact that the same hardware resources used for manufacturing test can be exploited for on-line test. Experimental results gathered on a case study system show the benefits and costs of the approach.

show abstract

“…Some approaches to detect NPSFs, such as the tiling method (Goor, 1991;Hayes, 1975), the two-group method (Goor, 1991;Hayes, 1980), the row-March algorithm (Franklin and Saluja, 1996), and a multi-background method (Cockburn, 1995;Yarmolik et al, 1998), have been proposed. The new publications deal with reduction in the costs of memory testing (Bernardi et al, 2006;Bernardi et al, 2005), fault detection by output response comparison of identical circuits using half-frequency compatible sequences (Pomeranz and Reddy, 2006), transparent memory testing (Li, 2007). Traditional March algorithms (Goor, 1991) have been widely used in memory testing because of their linear time complexity, high fault coverage, and ease in built-in self-test (BIST) implementation.…”

Section: Introductionmentioning

confidence: 99%

Address Sequences and Backgrounds with Different Hamming Distances for Multiple Run March Tests

Yarmolik¹

2008

International Journal of Applied Mathematics and Computer Science

View full text Add to dashboard Cite

It is widely known that pattern sensitive faults are the most difficult faults to detect during the RAM testing process. One of the techniques which can be used for effective detection of this kind of faults is the multi-background test technique. According to this technique, multiple-run memory test execution is done. In this case, to achieve a high fault coverage, the structure of the consecutive memory backgrounds and the address sequence are very important. This paper defines requirements which have to be taken into account in the background and address sequence selection process. A set of backgrounds which satisfied those requirements guarantee us to achieve a very high fault coverage for multi-background memory testing.

show abstract

Exploiting an Infrastructure IP to Reduce the Costs of Memory Diagnosis Costs in SoCs

Cited by 3 publications

References 19 publications

Embedded Memory Diagnosis: An Industrial Workflow

Embedded Memory Diagnosis: An Industrial Workflow

A New Architecture to Cross-Fertilize On-Line and Manufacturing Testing

Address Sequences and Backgrounds with Different Hamming Distances for Multiple Run March Tests

Contact Info

Product

Resources

About