Embedded Memory Diagnosis: An Industrial Workflow

Appello, D.; Tancorre, V.; Bernardi, P.; Grosso, M.; Rebaudengo, Maurizio; Reorda, Matteo Sonza

doi:10.1109/test.2006.297672

Cited by 18 publications

(9 citation statements)

References 26 publications

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“…an 8-bit microcontroller tested and diagnosed by means of SBST procedures [5] a 64Kx8 bit SRAM memory tested and diagnosed by means of a programmable BIST [4]. a 16x16 parallel multiplier tested and diagnosed by means of a Logic BIST and microcontroller implemented Soft-BIST approach [5].…”

Section: Case Study and Experimental Resultsmentioning

confidence: 99%

“…As an example, this is the case of memory cores equipped with diagnostic BIST [4]; figure 2 shows the flow for diagnosing a faulty memory core if the diagnostic BIST module can extract information about 1 failure per run. …”

Section: Figure 1: Transformation Of a Logic Bist Test Procedures Intomentioning

confidence: 99%

“…The collection of the overall diagnostic information is then used to built the failure bitmap and to attribute fault models to the failing cells[4].…”

mentioning

confidence: 99%

See 2 more Smart Citations

An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCs

Appello

Bernardi

Cagliesi³

et al. 2008

2008 13th European Test Symposium

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This paper describes a novel approach to enhance the process of reliability characterization for VLSI SoC products. To do this, we exploit Design for Test and Diagnosis structures in combination with new low-cost tester features and architecture. The main focus of our work is to obtain a modeling of the degradation of selected parameters measurable through at-speed testing.The paper reviews the current approach for reliability characterization and shows the achieved enhancement on efficiency and effectiveness. Results shown are related to experiments run on a vehicle released on a 90nm technology.

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Section: Case Study and Experimental Resultsmentioning

confidence: 99%

Section: Figure 1: Transformation Of a Logic Bist Test Procedures Intomentioning

confidence: 99%

See 1 more Smart Citation

An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCs

Appello

Bernardi

Cagliesi³

et al. 2008

2008 13th European Test Symposium

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show abstract

“…To the best of our knowledge, dynamic faults have been considered for diagnosis purpose in the literature only in [14], where the authors focus on dynamic coupling faults and extend the syndrome using the written data as field. Static faults have been more widely addressed [15,16,17]. These works propose the extension of the considered MT, by the addition of extra read operations, in order to increase the signature fields and therefore improve the DR.…”

Section: Signature-based Diagnosis Principlementioning

confidence: 99%

A Signature-based Approach for Diagnosis of Dynamic Faults in SRAMs

Ney

Bosio

Dilillo

et al. 2008

2008 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era

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This paper focuses on diagnosis of dynamic faults in SRAMs. The current techniques for fault diagnosis are mainly based on the signature method. Here, we introduce an extension of the signature scheme by taking in account additional information related to the addressing order during March test execution. A first advantage of the proposed approach is its capability to distinguish between static and dynamic faults. Another main feature is the correct identification of the location of the failure in a given memory component: the core-cell array, write drivers, sense amplifiers, address decoders and precharge circuits. Moreover, since this approach does not modify the March test, there is no increase of test complexity, conversely to other existing diagnosis techniques. * This work has been partially funded by the French government under the framework of the MEDEA+ 2A702 "NanoTEST" European program .

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“…For example, the fault dictionary, limited to stuck-at (SAF) and transition (TF) faults, for March C-, is given in Table 1 [6]. Based on this principle, most of existing studies on memory fault diagnosis target static faults such as stuck-at, transition and coupling faults [13,14,15]. Note that, static faults require a maximum of one operation (read or write) for their sensitization [1,16], while dynamic faults require more than one operation to be sensitized [10,16,17].…”

mentioning

confidence: 99%

A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs

Ney

Bosio

Dilillo

et al. 2008

2008 IEEE International Test Conference

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The usual techniques for memory diagnosis are mainly based on signature analysis. They consist in creating a fault dictionary that is used to determine the correspondence between the signature and the fault models affecting the memory. The effectiveness of such diagnosis methods is therefore strictly related to the fault dictionary accuracy. To the best of our knowledge, most of existing signature-based diagnosis approaches targets static faults only. In this paper, we present a new diagnosis approach that represents an alternative to signature-based approaches. This new diagnosis technique, named history-based diagnosis, makes use of the effect-cause paradigm already developed for logic design diagnosis. It consists in creating a database containing the history of operations (read and write) performed on a faulty memory core-cell. This information is crucial to track the root cause of the observed faulty behavior and it can be used to generate the set of possible Fault Primitives representing the set of suspected fault models. This new diagnosis method is able to identify static as well as dynamic faults. Although applied to SRAMs in this paper, it can be effective also for other memory types such as DRAMs. Experimental results are provided to prove the efficiency of the proposed methodology in generating a list of suspected faults as well as the location of the faulty components in the memory.

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Embedded Memory Diagnosis: An Industrial Workflow

Cited by 18 publications

References 26 publications

An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCs

An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCs

A Signature-based Approach for Diagnosis of Dynamic Faults in SRAMs

A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs

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