Bit‐area efficient embedded pseudo‐SRAM utilising dual‐threshold hybrid 2T gain cell

Abstract

The design and physical implementation of an embedded memory utilising bit-area efficient hybrid gain cell is presented. The memory cells in this work are composed of a high-threshold NMOS write transistor and a standard-threshold NMOS read transistor. The bit data are stored on the parasitic capacitances within the cells. Owing to the combination of low subthreshold-leakage write device and high mobility read device, this NMOS-based hybrid 2T gain cell exhibits much improved data retention and read performance in a compact bit area. The memory arrays operate with a logic-compatible supply voltage; SRAM-like I/O interface; chip-select-controlled 128-row refresh; and non-destructive read with speed comparable with 6T SRAM, but 65% smaller cell area. Measurement results from a 32 kbit pseudo-SRAM test chip implemented in a 130 nm logic CMOS technology demonstrate the effectiveness of the proposed embedded memory techniques.

Design optimisation procedure for digital mismatch compensation in latch comparators

“…This output signal is a NAND function of two internal signals S p28 and S p95 , which indicate when p reaches the codes p28 and p95, respectively. Stopm is then found as Stopm = S p28 S p95 (6) Similarly, Stopp is the digital signal generated by sequencer (−) to either enable or disable the increment of sequencer (+). It can be written in terms of the internal signals S m28 and S m95 , which indicate when m reaches the codes m28 and m95, respectively, as…”

“…Latch comparators, also known as regenerative comparators, are finding wide spread use in many high-performance systems such as analogue-to-digital converters (ADCs) [1][2][3] and static random access memory bit line detectors [4][5][6], as well as radio-frequency transceivers and low-power applications [7]. These dynamic circuits include positive feedback loops and provide high-speed operation, reduced silicon area and low-power consumption.…”

P‐channel logic 2 T eDRAM macro with high retention bit architecture

“…and the floating storage node. Especially, the write‐wordline deactivation is coupled to the storage node through the gate‐to‐source overlap capacitance of write‐transistor, affecting the bit storages significantly . This often causes a coupling loss on the data and degrades the bit retention considerably.…”

“…Especially, the write-wordline deactivation is coupled to the storage node through the gate-to-source overlap capacitance of write-transistor, affecting the bit storages significantly. 10 This often causes a coupling loss on the data and degrades the bit retention considerably. In order to resolve the limitation, our previous NMOS-only 2 T eDRAM in brief paper 14 has employed a more charge injection or beneficial capacitive-coupling technique without using optional devices.…”

“…The 2 T structure in mixed type of an n‐channel MOSFET and a p‐channel MOSFET also carries considerable bit‐area penalty due to the large well‐to‐well space. For the competitive bit‐area, the 2 T cell in the same type of MOSFETs could be the most effective option. Moreover, to obtain high data retention, PMOS‐only cells would be preferable because PMOS transistors have significantly lower leakage currents over their NMOS counterparts.…”