Bit error rate in NAND Flash memories

Mielke, N.; Marquart, Todd A.; Wu, Ning; Kessenich, J.; Belgal, H.; Schares, Eric; Trivedi, F.; Goodness, E.; Nevill, Leland R.

doi:10.1109/relphy.2008.4558857

Cited by 300 publications

(246 citation statements)

References 17 publications

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“…This scaling has been enabled due to continued reductions in the feature size of flash memory cells as well as the use of the multilevel cell (MLC) technology. Unfortunately, as feature size reduces (beyond 20nm today) and MLC technology is applied more aggressively, NAND flash memory cells become increasingly more subject to circuit level noise, leading to reduced reliability and endurance [15] [16]. As a result, more sophisticated mechanisms to tolerate (i.e., prevent and/or correct) errors become increasingly necessary.…”

Section: Introductionmentioning

confidence: 99%

“…Past works characterized flash memory errors into four types: erase, program interference, retention, and read [15] [16]. Retention errors, which occur due to flash cells gradually losing charge over time, were shown to be the dominant cause of errors in state-of-the-art MLC NAND flash memories, whereas program interference errors, which occur when the data stored in a cell/page changes unintentionally while a neighboring page is programmed, were shown to be the second dominant cause [15] [16].…”

Section: Introductionmentioning

confidence: 99%

“…Retention errors, which occur due to flash cells gradually losing charge over time, were shown to be the dominant cause of errors in state-of-the-art MLC NAND flash memories, whereas program interference errors, which occur when the data stored in a cell/page changes unintentionally while a neighboring page is programmed, were shown to be the second dominant cause [15] [16]. Building upon this understanding, we developed techniques to reduce retention errors by adaptively refreshing and correcting flash cells [12], showing that retention errors can be effectively mitigated.…”

Section: Introductionmentioning

confidence: 99%

“…Program interference is the phenomenon in which the threshold voltage of a flash cell, called the victim cell, unintentionally changes (i.e., gets disturbed) while another cell's value is being programmed [3][4] [15] [16]. This is due to parasitic capacitance coupling between neighboring cells, which gets worse as cells become closer to each other in distance with the reduction in feature size.…”

Section: Introductionmentioning

confidence: 99%

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Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation

Cai

Mutlu

Haratsch³

et al. 2013

2013 IEEE 31st International Conference on Computer Design (ICCD)

169

200

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Abstract-As NAND flash memory continues to scale down to smaller process technology nodes, its reliability and endurance are degrading. One important source of reduced reliability is the phenomenon of program interference: when a flash cell is programmed to a value, the programming operation affects the threshold voltage of not only that cell, but also the other cells surrounding it. This interference potentially causes a surrounding cell to move to a logical state (i.e., a threshold voltage range) that is different from its original state, leading to an error when the cell is read. Understanding, characterizing, and modeling of program interference, i.e., how much the threshold voltage of a cell shifts when another cell is programmed, can enable the design of mechanisms that can effectively and efficiently predict and/or tolerate such errors.In this paper, we provide the first experimental characterization of and a realistic model for program interference in modern MLC NAND flash memory. To this end, we utilize the read-retry mechanism present in some state-of-the-art 2Y-nm (i.e., 20-24nm) flash chips to measure the changes in threshold voltage distributions of cells when a particular cell is programmed. Our results show that the amount of program interference received by a cell depends on 1) the location of the programmed cells, 2) the order in which cells are programmed, and 3) the data values of the cell that is being programmed as well as the cells surrounding it. Based on our experimental characterization, we develop a new model that predicts the amount of program interference as a function of threshold voltage values and changes in neighboring cells. We devise and evaluate one application of this model that adjusts the read reference voltage to the predicted threshold voltage distribution with the goal of minimizing erroneous reads. Our analysis shows that this new technique can reduce the raw flash bit error rate by 64% and thereby improve flash lifetime by 30%. We hope that the understanding and models developed in this paper lead to other error tolerance mechanisms for future flash memories.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation

Cai

Mutlu

Haratsch³

et al. 2013

2013 IEEE 31st International Conference on Computer Design (ICCD)

169

200

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“…We choose a conservative baseline raw bit error rate (RBER) of 10 −8 , which comports with RBERs observed in Flash memory today [4,25].…”

Section: Mlc Model Parametersmentioning

confidence: 99%

Approximate storage in solid-state memories

Sampson

Nelson

Strauß

et al. 2013

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture

183

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Memories today expose an all-or-nothing correctness model that incurs significant costs in performance, energy, area, and design complexity. But not all applications need high-precision storage for all of their data structures all of the time. This paper proposes mechanisms that enable applications to store data approximately and shows that doing so can improve the performance, lifetime, or density of solid-state memories. We propose two mechanisms. The first allows errors in multi-level cells by reducing the number of programming pulses used to write them. The second mechanism mitigates wear-out failures and extends memory endurance by mapping approximate data onto blocks that have exhausted their hardware error correction resources. Simulations show that reduced-precision writes in multi-level phase-change memory cells can be 1.7× faster on average and using failed blocks can improve array lifetime by 23% on average with quality loss under 10%.

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Reliability Of Nand Flash Memory

Aritome¹

2015

Nand Flash Memory Technologies

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Bit error rate in NAND Flash memories

Cited by 300 publications

References 17 publications

Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation

Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation

Approximate storage in solid-state memories

Reliability Of Nand Flash Memory

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