Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation

Cai, Yu; Mutlu, Onur; Haratsch, Erich F.; Mai, Ken

doi:10.1109/iccd.2013.6657034

Cited by 169 publications

(206 citation statements)

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“…Therefore, if the number of read disturb errors can be dropped significantly by lowering V pass , the small number of read errors introduced may be warranted. 5 Naturally, this trade-off depends on the magnitude of these error rate changes. We now explore the gains and costs, in terms of overall RBER, for relaxing V pass below the maximum threshold voltage of a block.…”

Section: Effect Of Pass-through Voltage On Raw Bit Error Ratementioning

confidence: 99%

“…The four cells of our selected wordline turn their transistors off, off, on, and off, respectively, and we should read the correct data value 0010 from the LSBs. If V pass is set to 5V (higher than any of the threshold values of the block), the transistors for our unread 5 If too many read errors occur, we can always fall back to using the maximum threshold voltage for Vpass without consequence; see Sec. 4.4. cells are all turned on, allowing values from the wordline being read to pass through successfully.…”

Section: Effect Of Pass-through Voltage On Raw Bit Error Ratementioning

confidence: 99%

“…However, as its capacity increases, flash memory suffers from different types of circuitlevel noise, which greatly impact its reliability. These include program/erase cycling noise [2,3], cell-to-cell program interference noise [2,5,8], retention noise [2,4,6,7,23,24], and read disturb noise [11,14,24,33]. Among all of these types of noise, read disturb noise has largely been understudied in the past for MLC NAND flash, with no open-literature work available today that characterizes and analyzes the read disturb phenomenon.…”

Section: Introductionmentioning

confidence: 99%

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Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery

Cai

Luo

Ghose

et al. 2015

2015 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks

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166

183

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Abstract-NAND flash memory reliability continues to degrade as the memory is scaled down and more bits are programmed per cell. A key contributor to this reduced reliability is read disturb, where a read to one row of cells impacts the threshold voltages of unread flash cells in different rows of the same block. Such disturbances may shift the threshold voltages of these unread cells to different logical states than originally programmed, leading to read errors that hurt endurance.For the first time in open literature, this paper experimentally characterizes read disturb errors on state-of-the-art 2Y-nm (i.e., 20-24 nm) MLC NAND flash memory chips. Our findings (1) correlate the magnitude of threshold voltage shifts with read operation counts, (2) demonstrate how program/erase cycle count and retention age affect the read-disturb-induced error rate, and (3) identify that lowering pass-through voltage levels reduces the impact of read disturb and extend flash lifetime. Particularly, we find that the probability of read disturb errors increases with both higher wear-out and higher pass-through voltage levels.We leverage these findings to develop two new techniques. The first technique mitigates read disturb errors by dynamically tuning the pass-through voltage on a per-block basis. Using real workload traces, our evaluations show that this technique increases flash memory endurance by an average of 21%. The second technique recovers from previously-uncorrectable flash errors by identifying and probabilistically correcting cells susceptible to read disturb errors. Our evaluations show that this recovery technique reduces the raw bit error rate by 36%.

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Section: Effect Of Pass-through Voltage On Raw Bit Error Ratementioning

confidence: 99%

Section: Effect Of Pass-through Voltage On Raw Bit Error Ratementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery

Cai

Luo

Ghose

et al. 2015

2015 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks

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166

183

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“…Disturbance errors are a general class of reliability problem that afflicts not only DRAM, but also other memory and storage technologies: SRAM [16,26,40], flash [10,12,13,19,25], and hard-disk [36,63,68]. Van de Goor and de Neef [64] present a collection of production tests that can be employed by DRAM manufacturers to screen faulty chips.…”

Section: Other Related Workmentioning

confidence: 99%

Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors

Kim¹,

Daly²,

Kim³

et al. 2014

2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)

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449

1,019

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Abstract. Memory isolation is a key property of a reliable and secure computing system -an access to one memory address should not have unintended side effects on data stored in other addresses. However, as DRAM process technology scales down to smaller dimensions, it becomes more difficult to prevent DRAM cells from electrically interacting with each other. In this paper, we expose the vulnerability of commodity DRAM chips to disturbance errors. By reading from the same address in DRAM, we show that it is possible to corrupt data in nearby addresses. More specifically, activating the same row in DRAM corrupts data in nearby rows. We demonstrate this phenomenon on Intel and AMD systems using a malicious program that generates many DRAM accesses. We induce errors in most DRAM modules (110 out of 129) from three major DRAM manufacturers. From this we conclude that many deployed systems are likely to be at risk. We identify the root cause of disturbance errors as the repeated toggling of a DRAM row's wordline, which stresses inter-cell coupling effects that accelerate charge leakage from nearby rows. We provide an extensive characterization study of disturbance errors and their behavior using an FPGA-based testing platform. Among our key findings, we show that (i) it takes as few as 139K accesses to induce an error and (ii) up to one in every 1.7K cells is susceptible to errors. After examining various potential ways of addressing the problem, we propose a low-overhead solution to prevent the errors.

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“…Program interference errors will become aggressive when the programming operations are continually applied to a wordline. Vth distribution offset of flash cells in a page caused by the adjacent cells is greater than the far-neighbor cells [6], shown in Figure 3.…”

Section: Error Characterization Of Nand Flash Memorymentioning

confidence: 99%

Error Analysis and Adaptable Error-correct Scheme for NAND Flash Memory

Pan¹,

Liu²

2018

dtcse

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Abstract. With the continuous scaling of NAND flash memory process technology, the traditional solution for endurance enhancement is incapable of meeting the demands for NAND flash memory reliability. It's necessary to design an effective algorithm to overcome this problem. In this paper, we investigated the error characteristics under various types of flash operations to build a well understanding of the memory failure mechanism. On the foundation of the error analysis, we propose a new adaptive error correction algorithm. The algorithm can extend the lifetime of flash memory by employing error-correct methods adaptively with low hardware resource-cost.

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Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation

Cited by 169 publications

References 11 publications

Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery

Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery

Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors

Error Analysis and Adaptable Error-correct Scheme for NAND Flash Memory

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