Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision

Lee, Kyeongho; Jeong, Jinho; Cheon, Sungsoo; Choi, Woong; Park, Jongsun

doi:10.1109/dac18072.2020.9218567

Cited by 47 publications

(9 citation statements)

References 14 publications

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“…Therefore, it demonstrates a significant enhancement in energy efficiency, throughput, and latency. The various CiM architectures have been reported in the [13][14][15][16]. Most of the design for the CiM -based implemented system usually uses 6T SRAM cells [13,14].…”

Section: Introductionmentioning

confidence: 99%

Computing in-memory reconfigurable (accurate/approximate) adder design with negative capacitance FET 6T-SRAM for energy efficient AI edge devices

Venu,

Kadiyam,

Penumalli

et al. 2024

Semicond. Sci. Technol.

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Computing in-memory (CiM) is an alternative to von-Neumann architectures for energy efficient AI edge computing architectures with CMOS scaling. Approximate computing in-memory (ACiM) techniques have also been recently proposed to further increase the energy efficiency of such architectures. In the first part of the work, a Negative Capacitance FET (NCFET) based 6T-SRAM CiM accurate full adder has been proposed, designed and performance benchmarked with equivalent baseline 40nm CMOS design. Due to the steep slope characteristics of NCFET, at an increased ferroelectric layer thickness, Tfe of 3nm, the energy consumption of the proposed accurate NCFET based CiM design is ~82.48% lower in comparison to the conventional/Non CiM full adder design and ~ 85.27% lower energy consumption in comparison to the equivalent baseline CMOS CiM accurate full adder design at VDD = 0.5V. This work further proposes a reconfigurable computing in-memory NCFET 6T-SRAM full adder design (the design which can operate both in accurate and approximate modes of operation). NCFET 6T-SRAM reconfigurable full adder design in accurate mode has ~4.19x lower energy consumption and ~4.47x lower energy consumption in approximation mode when compared to the baseline 40nm CMOS design at VDD=0.5V, making NCFET based approximate CiM adder designs preferable for energy efficient AI edge CiM based computing architectures for DNN processing.

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Section: Introductionmentioning

confidence: 99%

Computing in-memory reconfigurable (accurate/approximate) adder design with negative capacitance FET 6T-SRAM for energy efficient AI edge devices

Venu,

Kadiyam,

Penumalli

et al. 2024

Semicond. Sci. Technol.

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“…Prior works [3,19,20,24,25,35] have shown that a simple change in the memory circuitry can enable tremendous in-memory computing potential. These works have proposed many ideas to allow in-memory computation in various memory technologies such as SRAM [17,34], DRAM [20,24], ReRAM [26,29], and STT-MRAM [3]. For instance, activating two wordlines in DRAM allows charge sharing among capacitors.…”

Section: Introductionmentioning

confidence: 99%

FAT-PIM: Low-Cost Error Detection for Processing-In-Memory

Zubair¹,

Jha²,

Mohaisen³

et al. 2022

Preprint

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Processing In Memory (PIM) accelerators are promising because they can provide massive parallelization and high efficiency in multiple application domains. These architectures can produce near-instantaneous results over wide data streams, allowing for real-time performance in data-intensive workloads. For instance, Resistive Memory (ReRAM) based PIM architectures are widely known for their inherent dot-product computation capability. While the performance of these architectures is appealing, reliability and accuracy are also important, especially in mission-critical real-time systems. Unfortunately, PIM architectures have a fundamental limitation in guaranteeing error-free operation. As a result, the current methods must pay high implementation costs or performance penalties to achieve reliable execution in the PIM accelerator. In this paper, we make a fundamental observation of this reliability limitation of ReRAM based PIM architecture. Accordingly, we propose a novel solution-Fault Tolerant PIM or FAT-PIM, that allows for low-cost error detection. Our evaluation using simulation technique shows that we can detect all errors with only 4.9% performance cost and 3.9% storage overhead.

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“…Many approaches to Logic-In-Memory can be found in literature; however, two main approaches can be distinguished. The first one can be classified as Near-Memory Computing (NMC) [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18], since the memory inner array is not modified and logic circuits are added at the periphery of this; the second one can be denoted as Logic-in-Memory (LiM) [19][20][21][22][23][24][25][26][27][28], since the memory cell is directly modified by adding logic circuits to it.…”

Section: Introductionmentioning

confidence: 99%

“…Many applications can benefit from the IMC approach, such as machine learning and deep learning algorithms [4,6,[8][9][10][11][12]14,15,19,[21][22][23][24], but also general purpose algorithms [2,5,7,13,[16][17][18]20,25,26]. For instance: in [19], a 6T SRAM cell is modified by adding two transistors and a capacitor to it, in order to perform analog computing on the whole memory, which allows to implement approximated arithmetic operations for machine learning algorithms; in [18], logic layers consisting of latches and LUTs are interleaved with memory ones in an SRAM array, in order to perform different kinds of logic operations directly inside the array; in [26], the pass transistors of the 6T SRAM cell are modified to perform logic operations directly in the cell, which allows the memory to function as an SRAM, a CAM (Content Addressable Memory) or a LiM architecture.…”

Section: Introductionmentioning

confidence: 99%

Custom Memory Design for Logic-in-Memory: Drawbacks and Improvements over Conventional Memories

et al. 2021

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The speed of modern digital systems is severely limited by memory latency (the “Memory Wall” problem). Data exchange between Logic and Memory is also responsible for a large part of the system energy consumption. Logic-in-Memory (LiM) represents an attractive solution to this problem. By performing part of the computations directly inside the memory the system speed can be improved while reducing its energy consumption. LiM solutions that offer the major boost in performance are based on the modification of the memory cell. However, what is the cost of such modifications? How do these impact the memory array performance? In this work, this question is addressed by analysing a LiM memory array implementing an algorithm for the maximum/minimum value computation. The memory array is designed at physical level using the FreePDK 45nm CMOS process, with three memory cell variants, and its performance is compared to SRAM and CAM memories. Results highlight that read and write operations performance is worsened but in-memory operations result to be very efficient: a 55.26% reduction in the energy-delay product is measured for the AND operation with respect to the SRAM read one. Therefore, the LiM approach represents a very promising solution for low-density and high-performance memories.

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Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision

Cited by 47 publications

References 14 publications

Computing in-memory reconfigurable (accurate/approximate) adder design with negative capacitance FET 6T-SRAM for energy efficient AI edge devices

Computing in-memory reconfigurable (accurate/approximate) adder design with negative capacitance FET 6T-SRAM for energy efficient AI edge devices

FAT-PIM: Low-Cost Error Detection for Processing-In-Memory

Custom Memory Design for Logic-in-Memory: Drawbacks and Improvements over Conventional Memories

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