Bit-serial multipliers and squarers

Ienne, Paolo; Viredaz, Marc A.

doi:10.1109/12.338107

Cited by 42 publications

(13 citation statements)

References 12 publications

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“…This would again lead to additional delay cycles in the mprod and euclidean operations, where the accumulation is performed on the longest data word of the system. An improved multiplication scheme was therefore developed for two's complement numbers [9]. The corresponding circuit is presented in Fig.…”

Section: Arithmetic Unitmentioning

confidence: 99%

GENES IV: A bit-serial processing element for a multi-model neural-network accelerator

Ienne

Viredaz

1995

Journal of VLSI Signal Processing

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Abstract.A systolic array of dedicated processing elements (PEs) is presented as the heart of a multi-model neural-network accelerator. The instruction set of the PEs makes possible to implement several widely-used neural models, including multi-layer Perceptrons with the back-propagation learning rule and Kohonen feature maps. Each PE holds an element of the synaptic weight matrix. An instantaneous swapping mechanism for the weight matrix makes the efficient implementation of neural networks larger than the physical PE array possible. A systolicallyflowing instruction accompanies each input vector propagating in the array. This avoids the need of emptying and refilling the array when the operating mode of the array is changed. Fixed point arithmetic is used in the PE. The problem of optimally scaling real variables in fixed-point format is addressed.Both the GENES IV chip, containing a matrix of 2 • 2 PEs, and an auxiliary arithmetic circuit have been manufactured and successfully tested. The MANTRA I machine has been built around these chips. Peak performances of the full system are between 200 and 400 MCPS in the evaluation phase and between 100 and 200 MCUPS during the learning phase (depending on the algorithm being implemented).

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Section: Arithmetic Unitmentioning

confidence: 99%

GENES IV: A bit-serial processing element for a multi-model neural-network accelerator

Ienne

Viredaz

1995

Journal of VLSI Signal Processing

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“…When analyzing the squarer in Fig. 2, it was found that the resemblance to a bit-serial squarer [6] [7] is large. By introducing registers in the design of the bit-serial squarer the partial results of x n 2 is easily extracted.…”

Section: B Processingmentioning

confidence: 99%

Parabolic synthesis methodology implemented on the sine function

Hertz

Nilsson

2009

2009 IEEE International Symposium on Circuits and Systems

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Abstract-This paper introduces a parabolic synthesis methodology for implementation of approximations of unary functions like trigonometric functions and logarithms, which are specialized for efficient hardware mapped VLSI design. The advantages with the methodology are, short critical path, fast computation and high throughput enabled by a high degree of architectural parallelism. The feasibility of the methodology is shown by developing an approximation of the sine function for implementation in hardware.

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“…This method needs only cells for an n-bit multiplication but it introduces an XOR gate in the critical path, which ends up with a more complicated overall design. Lenne et al [3] designed a bit-serial-serial multiplier that is modular in structure and can operate on both signed and unsigned numbers.…”

Section: Review Of Serial Multipliersmentioning

confidence: 99%

Design of Serial-Serial Multiplier based on the Asynchronous Counter Accumulation

Srikanth¹,

Kodam²

2014

IJCATR

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A system's performance is generally determined by the performance of the multiplier because the multiplier is generally the slowest clement in the system. Furthermore, it is generally the most area consuming. Hence, optimizing the speed and area of the multiplier is a major design issue. However, area and speed are usually conflicting constraints so that improving speed results mostly in larger areas. In this project we design a serial -serial multiplier based on the asynchronous counter accumulation. In this serialserial multiplier the number of sampling cycles is reduced to n from 2n by the reduction of partial products which is based on the asynchronous counters. It achieves high bit sampling rate by replacing conventional fulladder and highest 5:3 counters by simple asynchronous 1's counters so that the critical path is limited to only AND gate and D Flip-flops.

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Bit-serial multipliers and squarers

Cited by 42 publications

References 12 publications

GENES IV: A bit-serial processing element for a multi-model neural-network accelerator

GENES IV: A bit-serial processing element for a multi-model neural-network accelerator

Parabolic synthesis methodology implemented on the sine function

Design of Serial-Serial Multiplier based on the Asynchronous Counter Accumulation

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