BITMAN: A tool and API for FPGA bitstream manipulations

Pham, Khoa Dang; Horta, Edson Lemos; Koch, Dirk

doi:10.23919/date.2017.7927114

Cited by 47 publications

(13 citation statements)

References 14 publications

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“…Tools such as those in [34][35][36] offer advanced floor-planning and constraint generation during design flow and bitstream manipulation phases [37]. However, our approach utilizes the standard Xilinx flow as we only need to mask the static region and unmask the reconfigurable region which is available in a reset after reconfiguration (RAR)-supported partial bitstream.…”

Section: Cad Flowmentioning

confidence: 99%

VR-ZYCAP: A Versatile Resourse-Level ICAP Controller for ZYNQ SOC

et al. 2021

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Hybrid architectures integrating a processor with an SRAM-based FPGA fabric—for example, Xilinx ZynQ SoC—are increasingly being used as a single-chip solution in several market segments to replace multi-chip designs. These devices not only provide advantages in terms of logic density, cost and integration, but also provide run-time in-field reconfiguration capabilities. However, the current reconfiguration capabilities provided by vendor tools are limited to the module level. Therefore, incremental run-time configuration memory changes require a lengthy compilation time for off-line bitstream generation along with storage and reconfiguration time overheads with traditional vendor methodologies. In this paper, an internal configuration access port (ICAP) controller that provides a versatile fine-grain resource-level incremental reconfiguration of the programmable logic (PL) resources in ZynQ SoC is presented. The proposed controller implemented in PL, called VR-ZyCAP, can reconfigure look-up tables (LUTs) and Flip-Flops (FF). The run-time reconfiguration of FF is achieved through a reset after reconfiguration (RAR)-featured partial bitstream to avoid the unintended state corruption of other memory elements. Along with versatility, our proposed controller improves the reconfiguration time by 30 times for FFs compared to state-of-the-art works while achieving a nearly 400-fold increase in speed for LUTs when compared to vendor-supported software approaches. In addition, it achieves competitive resource utilization when compared to existing approaches.

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Section: Cad Flowmentioning

confidence: 99%

VR-ZYCAP: A Versatile Resourse-Level ICAP Controller for ZYNQ SOC

et al. 2021

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“…Various other methods also aimed to provide access to the configuration bits of an FPGA. JBits ™ (Guccione, Levi, & Sundararajan, 1999), XPART (Blodget, James-Roxby, Keller, McMillan, & Sundararajan, 2003) and BitMan (Pham, Horta, & Koch, 2017) provided an application program interface (API) with the Xilinx ® FPGA bitstream using high level programming languages such as Java ™ . Other attempts include the Debit-project (Note & Rannaud, 2008), the Bitfile interpretation library (Bil) (Benz, Seffrin, & Huss, 2012), PARBIT (PARtial BItfile Transformer) (Horta & Lockwood, 2001) and BitMaT (Bitstream Manipulation Tool) (Morford, 2005)-all of which were never fully completed.…”

Section: Manipulating Fpga Resourcesmentioning

confidence: 99%

Parsing and analysis of a Xilinx FPGA bitstream for generating new hardware by direct bit manipulation in real-time

Roux

Schoor

Vuuren

2019

SACJ

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Despite the many advantages run-time reconfiguration of FPGAs brings to the table, its usage is mostly limited to quasi-static applications. This is either due to the throughput of the reconfiguration process, or the time required to create new hardware. In order to optimise the former, the literature proposes a block RAM (BRAM)-based architecture in which a new configuration is stored in localised memory and reconfiguration is facilitated by a controller implemented in the FPGA fabric. The limitation of this architecture is that only a subset of configurations can be stored. When new hardware is required, the slow synthesis process (or a part thereof) has to be repeated for each new configuration. Various third-party tools aim to mitigate this overhead, but since the bitstream is shrouded in obscurity, all rely on a layer of abstraction that make them unusable in real-time. To address this issue, this paper presents a novel method to parse and analyse a Xilinx® FPGA bitstream to extract certain characteristics. It is shown how these characteristics could be used to design and implement a bitstream specialiser, capable of taking a bitstream and modifying the configuration bits of lookup tables in real-time.

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“…It maps technology mapped netlist to hypothetical FPGA specified by user. A low level bitstream manipulation tools BitMAT [7] and "BITMAN" [8] targeted Virtex-II FPGAs. A Java library named "abit" for direct manipulation of Atmel FPSLIC series bitstream and partial reconfiguration found in [9].…”

Section: Related Workmentioning

confidence: 99%

Configuration Bitstream Mapping with Programmable Resources on Spartan-3A FPGA using XDL and FAR

Matte¹,

Shah²

2018

IJET

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Configuration bitstream in FPGA is specific to vendor. It is difficult to understand bitstream format and eventually impossible to know how bits are placed in LUTs, flip flop, multiplexer, input and output interconnection network in FPGA. Normally user is not interested in knowing internals of FPGA, however it is believed that by opening the internals of FPGA, development would become very fast as it is achieved by open source community. In this paper we have proposed a simplified methodology to map configuration bitstream to its programmable resources targeting Spartan-3A FPGA. A simple AND gate design implemented in VHDL under different constraints. Correlation between different locations of AND gate is established with frame address register, XDL file report, FPGA editor and device view in PlanAhead. Keyword-Bitstream, Configuration memory, FPGA, FAR, NCD, XDL I. INTRODUCTION It is widely believed that the analysis of bitstream format is a tedious task. Increase in the complexity of digital circuit design demand for FPGA with more resources is increasing. FPGA has applications in wide variety of domains like space, telecommunications, networking, handheld devices etc. FPGA based industries demand CAD tools for design and development to meet time-to-market design metric. Like in open source communities, FPGAs development techniques are not open and certain things are vendor specific. Hence third party tools development has limited scope. If bitstream format would have been opened to users then possibility of cloning the device and IPs would have increased. Development on design tool side demands FPGAs internal details. Knowing FPGA bitstream definitely helps further development. Beside this, research communities and academicians are interested in knowing bitstream details. Limited work has been done in this direction. A bitstream is a file that contains programming information for an FPGA. FPGAs bitstream is generated by CAD tools and configures (reconfigures) resources on FPGA fabrics to implement desired design. Fig. 1 depicts general structure of bitstream file during configuration. Bitstream file is viewed as file containing header for device name, architecture, and date information. After the start header it has synchronization word, device identification along with various device initialization commands. Most of the data is for actual configuration of FPGA. Last part of bitstream again contains command registers like CRC, DESYNC etc. and then FPGA goes into start sequence operation. These details are contains in bitstream file. Each FPGA device has its own bitstream format to configure itself.

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BITMAN: A tool and API for FPGA bitstream manipulations

Cited by 47 publications

References 14 publications

VR-ZYCAP: A Versatile Resourse-Level ICAP Controller for ZYNQ SOC

VR-ZYCAP: A Versatile Resourse-Level ICAP Controller for ZYNQ SOC

Parsing and analysis of a Xilinx FPGA bitstream for generating new hardware by direct bit manipulation in real-time

Configuration Bitstream Mapping with Programmable Resources on Spartan-3A FPGA using XDL and FAR

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