Bitwise data parallelism in regular expression matching

Cameron, Rob; Shermer, Thomas C.; Shriraman, Arrvindh; Herdy, Kenneth S.; Lin, Dan; Hull, Benjamin R.; Meng, Lin

doi:10.1145/2628071.2628079

Cited by 15 publications

(3 citation statements)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…One study [40] presents an experimental evaluation of several FA models (NFAs, DFAs and A-DFAs) on CPUs with large pattern sets, reporting single-stream performance of 40 Mbps on a single-core Xeon E5620 processor. Others exploit SIMD execution on small pattern sets using efficient gather/scatter extension [69] and bit-parallel algorithm [70,71]. Recent work on small FSMs and inputs achieved 1.5 Gbps on a single CPU thread, but the challenges of large, complex FAs and data sets remain unaddressed [63].…”

Section: Related Work and Discussionmentioning

confidence: 99%

Fast support for unstructured data processing

You

Hoang

Becchi

et al. 2015

Proceedings of the 48th International Symposium on Microarchitecture

View full text Add to dashboard Cite

We propose the Unified Automata Processor (UAP), a new architecture that provides general and efficient support for finite automata (FA). The UAP supports a wide range of existing finite automata models (DFAs, NFAs, A-DFAs, JFAs, counting-DFAs, and countingNFAs), and future novel FA models. Evaluation on realistic workloads shows that UAP implements all models efficiently, achieving line rates 94.5% of ideal. A single UAP lane delivers line rates 50x greater than software approaches on CPUs and GPUs. Scaling UAP to 64 lanes achieves FA transition throughputs as high as 295 Gbps, more than 100x higher than CPUs and GPUs, and even exceeding ASIC approaches such as IBM's RegX by 6x. With efficient support for multiple input streams, UAP achieves throughputs that saturate even high speed stacked DRAM memory systems.The UAP design and implementation is efficient in instructions executed, memory references, and energy. UAP achieves a 1.2 Ghz clock rate (32nm TSMC CMOS), and a 64-lane UAP requires only 2.2 mm 2 and 563 mW. At these levels of performance and energy-efficiency, UAP is a promising candidate for integration into generalpurpose computing architectures.

show abstract

Section: Related Work and Discussionmentioning

confidence: 99%

Fast support for unstructured data processing

You

Hoang

Becchi

et al. 2015

Proceedings of the 48th International Symposium on Microarchitecture

View full text Add to dashboard Cite

show abstract

“…The result is returned to the processor. This feature occurs in multiple applications such as database management [17], DNA sequencing [18][19][20], and graph processing [21].…”

Section: B Potential Targeted Applicationsmentioning

confidence: 99%

Memristive devices for computation-in-memory

Nguyen

Xie

et al. 2018

2018 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

View full text Add to dashboard Cite

CMOS technology and its continuous scaling have made electronics and computers accessible and affordable for almost everyone on the globe; in addition, they have enabled the solutions of a wide range of societal problems and applications. Today, however, both the technology and the computer architectures are facing severe challenges/walls making them incapable of providing the demanded computing power with tight constraints. This motivates the need for the exploration of novel architectures based on new device technologies; not only to sustain the financial benefit of technology scaling, but also to develop solutions for extremely demanding emerging applications. This paper presents two computation-in-memory based accelerators making use of emerging memristive devices; they are Memristive Vector Processor and RRAM Automata Processor. The preliminary results of these two accelerators show significant improvement in terms of latency, energy and area as compared to today's architectures and design.

show abstract

“…Hardware-based automata can perform simultaneous and parallel exploration of all possible valid paths in an NFA, thereby achieving the processing complexity of a DFA without being subject to DFA state explosion. FPGAs offer the requisite parallelism and a number of relatively recent efforts have explored this direction [5,6,7,8,9]. However, the architectures based on NFA are limited by the capacity of FPGA chips since the transition table is mapped directly into the FPGA logic.…”

Section: Introductionmentioning

confidence: 99%

Automata Processor Architecture and Applications: A Survey

Almubarak¹,

Alshammeri²,

Ahmad

2016

IJGDC

View full text Add to dashboard Cite

Finite automata-based algorithms are becoming increasingly important for a wide range of application domains to process large volumes of unstructured data. Current processor technologies are not well suited to accelerate massively parallel operations related to the search and analysis of complex and unstructured data streams pattern identification problems. Hardware designers are exploring new processing technologies to accelerate pattern identification problems. One such technology is the recently introduced Micron Automata Processor (AP), which is a novel and powerful reconfigurable non-von Neumann processor that can be used for direct implementation of multiple Non-deterministic Finite Automata (NFAs) running concurrently on the same input stream. AP has a linear-scalable, two-dimensional MISD (Multiple Instruction Single Data) fabric comprised of thousands of interconnected small processing elements called State Transition Elements (STEs) to analyze complex data streams simultaneously to accelerate solving massively complex problems. The AP is promising future technology which provides new operations and new avenues for exploiting parallelism to accelerate the growing and important class of automata-based algorithms. In this paper, we present a survey of the state-of-the-art in automata processor based hardware accelerators. We describe AP hardware architecture, its programming environments, summarize its current successful applications in a wide range of diverse fields and explore future research trends and opportunities in this increasingly important area of automata computing paradigm.

show abstract

Bitwise data parallelism in regular expression matching

Cited by 15 publications

References 23 publications

Fast support for unstructured data processing

Fast support for unstructured data processing

Memristive devices for computation-in-memory

Automata Processor Architecture and Applications: A Survey

Contact Info

Product

Resources

About