BlackParrot: An Agile Open-Source RISC-V Multicore for Accelerator SoCs

Petrisko, Daniel; Gilani, Farzam; Wyse, Mark; Jung, Dai Cheol; Davidson, Scott; Gao, Paul; Zhao, Chun; Azad, Zahra; Canakci, Sadullah; Veluri, Bandhav; Guarino, Tavio; Joshi, Ajay; Oskin, Mark; Taylor, Michael

doi:10.1109/mm.2020.2996145

Cited by 45 publications

(21 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…SSR is necessary in both [19,27]. The wire overhead of each SSR is represented by N SSR in (1). N vnet and N port represent the number of virtual nets and the number of output ports.…”

Section: Wire Overheadmentioning

confidence: 99%

“…Instead, Network-on-Chip (NoC), a more flexible connection mechanism, is proposed to meet the performance demand in complex systems. With the help of NoC, networks in digital systems, such as many-core processors, could achieve extremely high bandwidth [1][2][3][4][5]. Inside a NoC, messages traverse from the source node to the destination node through many intermediate routers.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Latency-Optimized Network-on-Chip with Rapid Bypass Channels

Ma¹,

Gao²,

Gao³

et al. 2021

Micromachines

View full text Add to dashboard Cite

Network-on-Chips with simple topologies are widely used due to their scalability and high bandwidth. The transmission latency increases greatly with the number of on-chip nodes. A NoC, called single-cycle multi-hop asynchronous repeated traversal (SMART), is proposed to solve the problem by bypassing intermediate routers. However, the bypass setup request of SMART requires additional pipeline stages and wires. In this paper, we present a NoC with rapid bypass channels that integrates the bypass information into each flit. In the proposed NoC, all the bypass requests are delivered along with flits at the same time reducing the transmission latency. Besides, the bypass request is unicasted in our design instead of broadcasting in SMART leading to a great reduction in wire overhead. We evaluate the NoC in four synthetic traffic patterns. The result shows that the latency of our proposed NoC is 63.54% less than the 1-cycle NoC. Compared to SMART, more than 80% wire overhead and 27% latency are reduced.

show abstract

“…SSR is necessary in both [19,27]. The wire overhead of each SSR is represented by N SSR in (1). N vnet and N port represent the number of virtual nets and the number of output ports.…”

Section: Wire Overheadmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Latency-Optimized Network-on-Chip with Rapid Bypass Channels

Ma¹,

Gao²,

Gao³

et al. 2021

Micromachines

View full text Add to dashboard Cite

show abstract

“…In addition to FPGA based platforms for rapid prototyping and evaluation, several many-core architectures that target ASIC platforms for low power and energy consumption requirements have been developed. In this context, Black-Parrot [18] is proposed as modular low power RISC-V based multi-core architecture. The architecture is specified as a heterogeneous tile-based architecture similar to the ESP platform proposed by [9], [10] which also maintain data coherency between the RISC-V and accelerators tiles.…”

Section: Related Work and Backgroundmentioning

confidence: 99%

Towards a Modular RISC-V Based Many-Core Architecture for FPGA Accelerators

2020

View full text Add to dashboard Cite

Multi-/Many-core architectures are emerging as scalable, high-performance and energy-efficient computing platforms suitable for a variety of application domains from edge to cloud computing. Recently, the appearance of RISC-V open-source ISA creates new possibilities to develop customized computing platforms with high savings in the non-recurring engineering costs. Moreover, the current trends toward open-source hardware frameworks are aimed to reduce design time and cost for complex system-on-chip architectures. Therefore, modularity and re-usability of hardware components are major challenges for flexible hardware architectures. The motivation behind this work is to introduce a modular cluster-based many-core architecture for FPGA accelerators that is re-usable and flexible tailored to implement different many-core taxonomies with less design time and costs by using regular and replicated sets of computing, memory, and interconnection blocks. The proposed many-core architecture is built using multiple processing clusters coupled with a NoC for communication which allows a high degree of design scalability. The processing cluster inside features a configurable multi-core architecture consisting of multiple RISC-V processing elements (PE) tightly coupled with a bus-based interconnection for intra-cluster communication using parameterized scratchpad shared memory. Each PE features a single RISC-V core with a tightly coupled parameterized scratchpad local memory and generic AXI interface. Evaluation results demonstrate that the proposed architecture features a scalable computing performance of 501 MOp/s for 4 clusters and 878 MOp/s for 8 clusters. Moreover, a scalable memory bandwidth up to 4.3 GB/s is achieved for 9 clusters with a power consumption of 1.4 W per cluster utilizing 7.7% of on-chip memory resources. The many-core architecture is implemented and evaluated on Xilinx Virtex Ultrascale+ with the feature of changing the architecture configurations during run-time using dynamic and partial reconfiguration which provides more flexibility and re-usability.INDEX TERMS Many-core architecture, parallel computing, RISC-V, network-on-chip (NoC), field programmable gate array (FPGA), reconfigurable computing.

show abstract

“…RISC-V Cores. Moreover, we have Linux-capable implementations of RISC-V processors like BlackParrot [22], ETH Zurich Ariane [29], and Berkeley Rocket [11], as well as GP-GPU-style compute throughput fabrics like HammerBlade Manycore [8] (descended from Celerity [9,14,23]), microcontrollers like Western Digital's SweRV [3], and scalable multicore server processors like the RISC-V incarnation of Princeton OpenPiton [12]. RISC-V unlocking research and education.…”

Section: Risc-vmentioning

confidence: 99%

“…The HammerBlade RISC-V ML/Graphs system reaches toward the end user by implementing the CUDA-lite language, and by supporting PyTorch. The BlackParrot [22] system has a ready-built SDK, and accelerator integration guide that allows for fast accelerator/SoC composition. How will you discover what systems might be built with your agile HW?…”

Section: Open Source Ipmentioning

confidence: 99%