Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integration

Dynamic fine-grain leakage reduction using leakage-biased bitlines

“…One DDFT technique, popular in low-power processors for portable devices, is a dynamically varying body bias to modulate transistor threshold voltages [24,29,13,11,16]. Reverse body biasing, by setting the p-well voltage higher than Vdd and the n-well voltage lower than GND, increases V T because of the body effect, thereby reducing leakage current.…”

“…An alternative DDFT approach is power gating [24,29,13,11,16]. The power supply to circuits can be cut off by inserting a high V T sleep transistor between Vdd and virtual Vdd (or GND and virtual GND).…”

“…Some of the disadvantages of sleep transistors are that they add additional impedance in the power supply network which reduces circuit speed, they require additional area and routing resources for the virtual power supply nets, and they may consume considerable deactivation energy to switch between active and inactive states. By sizing the sleep transistor [13], boosting the gate voltage for the sleep transistor [11], or forward-biasing the sleep transistor [16], the delay penalty can be reduced in exchange for greater sleep leakage currents and increased deactivation energy.…”

“…Techniques that trade increased circuit delay for reduced leakage current include: conventional transistor sizing, lower Vdd [32,30], stacked gates [25,35,9], longer channels [23], higher threshold voltages [19,34,21,13,1], and thicker T ox ; we collectively refer to these as statically-selected slow transistors (SSSTs). Techniques for dynamic run-time deactivation of fast transistors include body biasing [24,17,18,20,15], sleep transistors [24,29,13,11,16], and sleep vectors [35,9]; we collectively refer to these as dynamically-deactivated fast transistors (DDFTs). SSSTs and DDFTs are complementary approaches: SSSTs reduce leakage on non-critical paths and DDFTs reduce leakage on critical paths.…”

Power Valve: for low power operation and low stand-by power

“…To reduce the leakage current in stand-by mode, some researches have been reported switch transistor techniques, such as MTCMOS [1] or Boosted-Sleep [2].…”