Boosting single-thread performance in multi-core systems through fine-grain multi-threading

Abstract

Industry has shifted towards multi-core designs as we have hit the memory and power walls. However, single thread performance remains of paramount importance since some applications have limited thread-level parallelism (TLP), and even a small part with limited TLP impose important constraints to the global performance, as explained by Amdahl's law.In this paper we propose a novel approach for leveraging multiple cores to improve single-thread performance in a multi-core design. The proposed technique features a set of novel hardware mechanisms that support the execution of threads generated at compile time. These threads result from a fine-grain speculative decomposition of the original application and they are executed under a modified multi-core system that includes: (1) mechanisms to support multiple versions; (2) mechanisms to detect violations among threads; (3) mechanisms to reconstruct the original sequential order; and (4) mechanisms to checkpoint the architectural state and recovery to handle misspeculations.The proposed scheme outperforms previous hardware-only schemes to implement the idea of combining cores for executing single-thread applications in a multi-core design by more than 10% on average on Spec2006 for all configurations. Moreover, single-thread performance is improved by 41% on average when the proposed scheme is used on a Tiny Core, and up to 2.6x for some selected applications.

R3-DLA (Reduce, Reuse, Recycle): A More Efficient Approach to Decoupled Look-Ahead Architectures

“…Obtaining addresses through partial execution of the program represents a broad class of prefetching approaches. On one extreme of the design spectrum, many short threads are launched as helpers to precompute information for data or instruction supply [4], [6], [16]- [20], [24]- [26], [29], [32], [52]- [54], [63], [65]- [67], [72], [86]- [88], [98], [106], [107], [111], [114]. Although these micro helper threads are an immensely useful concept, marshalling a very large number of micro threads can bring practical issues: i) They are largely hand crafted and carefully inserted at the right locations, perhaps after lengthy trialand-errors.…”

A Case for a More Effective, Power-Efficient Turbo Boosting

“…Various flavors of helper threading have been proposed in the past. Micro helper threading [4,16,21,30,43,47,48,52,53,60,73,74] launches short threads ahead of potentially stalling instructions to avoid performance bottlenecks. These threads include specific instructions (often identified via lengthy manual tuning) required to precompute address or branch direction in a timely manner.…”

Performance-optimum superscalar architecture for embedded applications

“…Recently multiprocessors, very long instruction word (VLIW) and multi-issue superscalar processors satisfy the high performance requirements. However, these architectures have complex design flows [3][4][5][6][7]. Multiprocessors are most often used in recent researches [4][5][6][8][9][10][11].…”

“…However, these architectures have complex design flows [3][4][5][6][7]. Multiprocessors are most often used in recent researches [4][5][6][8][9][10][11].…”

“…Dynamic sharing method has been used in [14,21,22] in which threads participate in a competition for accessing the recourses. Static approaches have also been used by designers in which each thread has dedicated recourses and in comparison, static approaches are better than dynamic approaches when the number of threads is low and chip resources do not have a limited budget [6,8,11]. An appropriate approach to implement a multi-thread chip is re-implementing a single thread processor with multiple threads.…”