Bootstrap Voltage and Dead Time Behavior in GaN DC–DC Buck Converter With a Negative Gate Voltage

Performance improvement of DC‐DC converter using L‐D‐based modified GaN‐FET driver

“…From the simulation study, it is found that during switch OFF time, the voltage across drain to source will rise at the top switch of GaN‐FET‐based synchronous buck converter. Now from Figure 10A‐C, it is clear that immunity of the top switch at turn‐OFF time is more in proposed GaN‐FET driver compared with others like fromo Roschatt et al 10 and the TI‐based GaN‐FET driver. Therefore, the possibility of false turn ON during turn OFF time can be effectively eliminated by L‐D‐based GaN‐FET driver with negative bias.…”

“…EPC2110 GaN FET drain to source voltage using (A) TI driver, (B) driver proposed by Roschatt et al, 10 and (C) using the proposed driver. EPC2110 GaN FET gate to source voltage using (D) the proposed GaN driver, (E) driver proposed by Roschatt et al, 10 and (F) GaN‐based synchronous buck converter with DSP board TMS320F28379D [Colour figure can be viewed at wileyonlinelibrary.com]…”

“…This also limits the transient performance expected from the GaN‐FET‐based DC‐DC converter. There are two approaches found in the literature to address these issues: (a) using a negative‐biased gate driver and 9 (b) using an inductor‐based driver circuit 10 …”

Reduction of oscillations in a GaN bridge leg using active gate driving with sub-ns resolution, arbitrary gate-resistance patterns

“…An anti-parallel Schottky diode is placed across to reduce the conduction loss [13]. However, the parasitic inductances of the diode together with the additional parasitic capacitance it adds to may lead to more oscillation in the rising edge of 2 [14]. An RC snubber is one option to damp the oscillation observed on the rising edge of 2 , however efficiency is reduced as a result.…”

Multi-physic Analysis for GaN Transistor PCB Layout

“…For the optimal gate layout design, loop inductance must be minimized to avoid gate over voltage during turn-on transient and unintentional triggered-on during turn-off transient [6] [7]. The phenomenon of gate unintentional triggered can be further suppressed by applying negative gate voltage, while extra reverse conduction loss is introduced [8] [9]. Moreover, cross talk in GaN transistor totem pole should also be avoided by low capacitance design in gate loop layout and appropriate gate resistor selection [10] [11].…”