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The low threshold voltage of Gallium Nitride enhancement mode FETs is a concern in high current high frequency synchronous DC-DC buck converters. Applying a negative gate voltage to the low side FET to improve the dV/dt robustness increases the voltage drop between source and drain during dead-time conduction. This has consequences not only on the efficiency, but more importantly on the bootstrap voltage. Even with precise dead-timing, the large voltage drop from drain to source still results in a significant variation of the bootstrap voltage. This results in a change of gate turn on speed and increases the dV/dt stress. The very short dead-time needed to avoid great variations in the bootstrap voltage means that the voltage drop from source to drain can no longer bet treated as a constant as it varies greatly during the dead-time.

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