Bottom-up filling of Through Silicon Via (TSV) with Parylene as sidewall protection layer

Miao, Min; Zhu, Yunhui; Ji, Ming; Ma, Shenglin; Sun, Xiankai; Jin, Yufeng

doi:10.1109/eptc.2009.5416507

Cited by 15 publications

(4 citation statements)

References 5 publications

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“…As a room temperature chemical vapor deposition, it will not lead to wet contamination during the manufacturing process. Also, it is more compatible than other organic materials [20]. In addition, the Parylene could be conformal and pin-hole-free deposited.…”

Section: Introductionmentioning

confidence: 99%

Optimized chemical mechanical polishing of Parylene C for high-density wiring in flexible electronics

Chen¹,

Han²,

Xiao³

et al. 2022

Flex. Print. Electron.

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With the rapid development of flexible electronics, an increasing number of microfabrication strategies originating from the Si-based integrated circuits field have been explored on organic materials. Parylene C, a polymer, has been widely used in the microelectromechanical systems (MEMS) field because of its outstanding fabrication merits, such as room-temperature processability, conformal coating, and precise thin film deposition capability with the thickness tunable from 1 nm to 100 μm. As a good dielectric material, the Parylene C is also suitable for interlayer dielectrics (ILD) in flexible electronics. This study develops an optimized chemical mechanical polishing (CMP) technique of Parylene C for high-density redistribution wiring in high-performance flexible electronics. The roughness of the Parylene C surface after CMP was as low as 14.3±1.5 Å. The problems of slurry pollution and mechanical failure of the Parylene film that degrade the dielectric performance of the Parylene C could be avoided by taking the optimized CMP method. The multi-material structure constructed by Parylene C, Silicon and electroplated Copper was prepared and polished using the optimized CMP process. Additionally, a flexible wiring sample has been successfully patterned by the Damascene process through the optimized CMP process. In this sample, both the distance between each wire and the wire width were as small as 5 μm.The optimized Parylene C CMP process is easy-to-realize, highly efficient, low cost, and with minor defects; it provides a promising way to achieve high-density interconnection in high-performance flexible electronic devices.

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Section: Introductionmentioning

confidence: 99%

Optimized chemical mechanical polishing of Parylene C for high-density wiring in flexible electronics

Chen¹,

Han²,

Xiao³

et al. 2022

Flex. Print. Electron.

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“…3D memory chip module is one of the promising 3D-TSV integration applications, which can largely reduce the chip area and is helpful to performance improvement and cost reduction [4], [5]. Recently, variety of 3D-TSV integration approaches for 3D memory module, including DRAM and NAND Flash, has been reported [6][7][8][9][10]. In a 3D memory module, most I/O signals of a memory chip, including address bus, data bus, power, read and write control, are common signals, and could be shared with other memory chips in the module.…”

Section: Introductionmentioning

confidence: 99%

Development and characterization of a through-multilayer TSV integrated SRAM module

Zhu

Sun

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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In this study, a stacked SRAM module with a built-in decoder was proposed with a through-multilayer TSV integration process. The through-multilayer TSVs provided data passages for all common signals, including the address bus, data bus, power, read and write control, which were redistributed at each individual chip, while the chip select signals were connected separately to the built-in decoder. Regarding this process, a novel double-layer spin coating technology was employed to prevent photoresist residue left inside TSVs, and the RDLs in this process could be fabricated using lift-off process prior to via filling. As a result, the front side CMP process was not necessary. A 10-layer throughmultilayer TSV integration sample was successfully fabricated with this process. Preliminary testing results suggested that this process was promising for integration of memory chips with similar layout. Background3D integration using through silicon via (TSV) has many advantages, such as high packaging density, small form factor and high bandwidth due to the short connection lengths [1-3]. 3D memory chip module is one of the promising 3D-TSV integration applications, which can largely reduce the chip area and is helpful to performance improvement and cost reduction [4], [5]. Recently, variety of 3D-TSV integration approaches for 3D memory module, including DRAM and NAND Flash, has been reported [6-10]. In a 3D memory module, most I/O signals of a memory chip, including address bus, data bus, power, read and write control, are common signals, and could be shared with other memory chips in the module. Considering of this feature of 3D memory module, in this paper, we have proposed a simplified through-multilayer TSV integration process aiming at stacked SRAM module. A stacked SRAM module has been designed using commercial 2D EDA tools, which simplified the complexity of 3D module design, meanwhile took the technical advantages of 3D integration. The feature of this TSV integration process was RDL formation prior to TSV filling. Thus front side planarization by CMP (Chemical Mechanical Polishing) process after TSV filling was not necessary. With this process, a 10-layer TSV integration sample was successfully fabricated.

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“…Parylene-N has been investigated as an insulation layer in the TSV structures [7]. Parylene-C also has been used in the process of TSV copper electroplating filling, as sidewall protection to ensure bottom-up filling of blind TSV [8]. Parylene-HT, the newest parylene material with the lowest dielectric constant and highest temperature tolerance among the commercially available variant of Parylene-N, -C, -D and -HT, would be a candidate as insulation layer/liner for TSV application by means of vapor phase polymerization at low temperatures [9].…”

Section: Introductionmentioning

confidence: 99%

Copper filled TSV formation with Parylene-HT insulator for low-temperature compatible 3D integration

Thanh

Cheng

Watanabe

et al. 2014

2014 International 3D Systems Integration Conference (3DIC)

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In this paper, investigation of Parylene-HT for using as insulation/liner in through-silicon-via (TSV) is presented. Bottom-up copper filled TSVs with 1 µm Parylene-HT insulator with aspect ratios (ARs) up to 10, are demonstrated on a 100 µm-thick Si wafer through via etching, parylene vapor deposition, and copper electroplating processes. Cross sectional inspections on the fabricated TSVs confirm the pin-hole free, high-uniformity, good conformal coverage room temperature deposited Parylene-HT liner, the void-and seam-free filled Cu, as well as the low diffusivity of Cu into Parylene-HT. Excellent insulation function of Parylene-HT liner, i.e., capacitance of 0.164 pF/TSV and leakage current density of 22 pA/cm 2 at a field of 0.25 MV/cm, were also confirmed on the fabricated TSV. As the Parylene-HT deposition and Cu electroplating processes can be implemented at room temperature, the copper filled TSV formation with Parylene-HT insulator investigated in this work is highly compatible with low-temperature 3D integration.

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Bottom-up filling of Through Silicon Via (TSV) with Parylene as sidewall protection layer

Cited by 15 publications

References 5 publications

Optimized chemical mechanical polishing of Parylene C for high-density wiring in flexible electronics

Optimized chemical mechanical polishing of Parylene C for high-density wiring in flexible electronics

Development and characterization of a through-multilayer TSV integrated SRAM module

Copper filled TSV formation with Parylene-HT insulator for low-temperature compatible 3D integration

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