Development and characterization of a through-multilayer TSV integrated SRAM module

Abstract

In this study, a stacked SRAM module with a built-in decoder was proposed with a through-multilayer TSV integration process. The through-multilayer TSVs provided data passages for all common signals, including the address bus, data bus, power, read and write control, which were redistributed at each individual chip, while the chip select signals were connected separately to the built-in decoder. Regarding this process, a novel double-layer spin coating technology was employed to prevent photoresist residue left inside TSVs, and the RDLs in this process could be fabricated using lift-off process prior to via filling. As a result, the front side CMP process was not necessary. A 10-layer throughmultilayer TSV integration sample was successfully fabricated with this process. Preliminary testing results suggested that this process was promising for integration of memory chips with similar layout. Background3D integration using through silicon via (TSV) has many advantages, such as high packaging density, small form factor and high bandwidth due to the short connection lengths [1-3]. 3D memory chip module is one of the promising 3D-TSV integration applications, which can largely reduce the chip area and is helpful to performance improvement and cost reduction [4], [5]. Recently, variety of 3D-TSV integration approaches for 3D memory module, including DRAM and NAND Flash, has been reported [6-10]. In a 3D memory module, most I/O signals of a memory chip, including address bus, data bus, power, read and write control, are common signals, and could be shared with other memory chips in the module. Considering of this feature of 3D memory module, in this paper, we have proposed a simplified through-multilayer TSV integration process aiming at stacked SRAM module. A stacked SRAM module has been designed using commercial 2D EDA tools, which simplified the complexity of 3D module design, meanwhile took the technical advantages of 3D integration. The feature of this TSV integration process was RDL formation prior to TSV filling. Thus front side planarization by CMP (Chemical Mechanical Polishing) process after TSV filling was not necessary. With this process, a 10-layer TSV integration sample was successfully fabricated.

Mechanical and electrical reliability assessment of bump-less wafer-on-wafer integration with one-time bottom-up TSV filling

“…The average resistance of daisy chain containing 2 TSVs, 4 TSVs, 6 TSVs and 14 TSVs was 152.06mΩ, 378.45mΩ, 660.42mΩ and 1570.87mΩ respectively. The average resistance of K1 was 23.12% less than the four-layer stacked structure containing bumps we previously reported [7]. Fig.3 illustrated the surface and cross section image of bump-less integration, no significant crack or delamination was observed and no obvious stress was measured due to the room temperature stress relaxation.…”

Research on transmission and crosstalk characteristics of a new type of through silicon via and multilayer through silicon via

“…Much work has been done to explore the electrical property of different TSV structures. Figure 17 showed three types of multilayer TSV structures [17,18], which were modeled in HFSS respectively. Different layers of TSVs were connected by 0.5um copper columns (or copper rings), as shown in Figure 18.…”