Mechanical and electrical reliability assessment of bump-less wafer-on-wafer integration with one-time bottom-up TSV filling

Abstract

Three-dimensional (3D) stacked memory module based on TSV is becoming an attractive alternative. Chips are assembled through micro bumps, which will bring additional thermo-mechanical stress, as well as the channel resistance and interconnection reliability problem. In this paper, we leverage thermal cycles to assess the mechanical and electrical reliability of a bump-less wafer-on-wafer integration approach with one-time bottom-up TSV filling we reported. Resistance was measured by four-point probes test after 10, 20, 40, 80, 160, 240, 320..., until 640 thermal cycles. Part of fixed TSVs' morphology was observed through scanning electron microscope (SEM) and stress was qualitative characterized by an infrared photo elastic system during thermal cycles. What's more, a thermo-mechanical finite element model (FEM) simulation was discussed, which showed that there was little difference in stress, strain, and copper extrusion values at lower temperature. All test results supported the good mechanical and electrical behavior of this bump-less waferon-wafer integration approach.