Breakdown Analysis of Magnetic Flip-Flop With 28-nm UTBB FDSOI Technology

Cai, Hao; Wang, You; Naviner, Lírida Alves de Barros; Zhao, Weisheng

doi:10.1109/tdmr.2016.2584140

Cited by 12 publications

(4 citation statements)

References 38 publications

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“…The reliability of hybrid CMOS/magnetic integration is a major concern for circuit designers in the near future [43][44][45][46][47][48][49]. The integration of unreliable, deep-scaled nanometer CMOS and MTJ processes pose tremendous challenges from the device level up to system level.…”

Section: Discussionmentioning

confidence: 99%

“…With the continuous scaling of CMOS technology nodes, MRAM with design-for-reliability is required due to the impacts of parametric process variations, aging mechanisms and transient faults [35,36,[45][46][47][48]. In this section, the process variation, thermal variation and breakdown are reviewed for reliable MRAM design.…”

Section: Reliability Issuesmentioning

confidence: 99%

“…The stress voltage applied on MTJ oxide barrier is around 400 mV, whereas CMOS transistor is biased with 1 V gate voltage. The MTJ oxide barrier thickness is lower than FD-SOI CMOS oxide, which is around 1 nm [46]. The probability of breakdown occurrence in CMOS devices follows the Weibull distribution [47].…”

Section: Dielectric Breakdownmentioning

confidence: 99%

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High Performance MRAM with Spin-Transfer-Torque and Voltage-Controlled Magnetic Anisotropy Effects

Cai

Wang²,

Wang

et al. 2017

Applied Sciences

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Featured Application: Non-volatile magnetic tunnel junction-based magnetoresistive random access memory as reliable, high energy efficiency Internet of Things (IoTs) node memory.Abstract: The Internet of Things (IoTs) relies on efficient node memories to process data among sensors, cloud and RF front-end. Both mainstream and emerging memories have been developed to achieve this energy efficiency target. Spin transfer torque magnetic tunnel junction (STT-MTJ)-based nonvolatile memory (NVM) has demonstrated great performance in terms of zero standby power, switching power efficiency, infinite endurance and high density. However, it still has a big performance gap; e.g., high dynamic write energy, large latency, yield and reliability. Recently, voltage-controlled magnetic anisotropy (VCMA) has been introduced to achieve improved energy-delay efficiency and robust non-volatile writing control with an electric field or a switching voltage. VCMA-MTJ-based MRAM could be a promising candidate in IoT node memory for high-performance, ultra-low power consumption targets.

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Section: Discussionmentioning

confidence: 99%

Section: Reliability Issuesmentioning

confidence: 99%

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High Performance MRAM with Spin-Transfer-Torque and Voltage-Controlled Magnetic Anisotropy Effects

Cai

Wang²,

Wang

et al. 2017

Applied Sciences

Self Cite

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“…MTJ-based low power nonvolatile flip-flops [14], [18] are being used in the latest highperformance System on Chip (SoC) applications [22], [23]. Spin Transfer Torque (STT) based multi-bit nonvolatile flipflops [15], [19] are being used for non-volatile storage applications. Energy and area efficient SOT based Nonvolatile flip flop for power-gating [16] are employed in the latest SoC applications.…”

Section: Electrical Controlled Magnetic Tunnel Junction (Mtj)mentioning

confidence: 99%

Spin-Orbit-Torque Magnetic Tunnel Junction Transistor Based Area Efficient Low Power Non-Volatile Master-Slave Flip-Flop

Nisha¹

2020

IJETER

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A Spin Orbit Torque (SOT) Magnetic-Tunnel-Junction (MTJ) transistor based area efficient F) is discussed in this paper. The modified NV-MSFF has consumed less area and less power consumption when compared to the existing NV-MSFF. Hence, the proposed NV-MSFF is more suitable for low power applications. The proposed NV-MSFF is designed and implemented as hybrid CMOS-Spintronics circuit using 45 nm CMOS process technology and Verilog-A model based MTJ-Transistor for Spintronics. The proposed NV-MSFF has been designed and simulated using Cadence Virtuoso-Analog-Design-Environment (ADE) with Spectre as the simulator and the simulation temperature as 27°C. The proposed NV-MSFF has 44% reduction in the area occupied. The overall energy requirement of the prevailing NV-MSFF is 1.961 µW whereas it is 194.2 nW only for modified NV-MSFF. The delay of the existing NV-MSFF is 1.175 ns whereas it is 383.3 ps only for the modified NV-MSFF. The proposed NV-MSFF outperforms in terms of area, power and the propagation time.

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Designing low power magentic flip flop in 45 nm FDSOI technology for large scale cluster based engineering application

Sakthimurugan¹,

Geetha

2018

Cluster Comput

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Breakdown Analysis of Magnetic Flip-Flop With 28-nm UTBB FDSOI Technology

Cited by 12 publications

References 38 publications

High Performance MRAM with Spin-Transfer-Torque and Voltage-Controlled Magnetic Anisotropy Effects

High Performance MRAM with Spin-Transfer-Torque and Voltage-Controlled Magnetic Anisotropy Effects

Spin-Orbit-Torque Magnetic Tunnel Junction Transistor Based Area Efficient Low Power Non-Volatile Master-Slave Flip-Flop

Designing low power magentic flip flop in 45 nm FDSOI technology for large scale cluster based engineering application

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