BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W

Ando, Keiichi; Ueyoshi, Kodai; Orimo, Kentaro; Yonekawa, Haruyoshi; Sato, Shusei; Nakahara, Hiroki; Takamaeda-Yamazaki, Shinya; Ikebe, Masayuki; Asai, Tetsuya; Kuroda, Tadahiro; Motomura, Masato

doi:10.1109/jssc.2017.2778702

Cited by 136 publications

(62 citation statements)

References 10 publications

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“…YodaNN [34] targets binary-weight networks and reaches energy efficiency up to 61 Top/s/W. Other accelerators exploit extreme quantization for the deployment of binary neural networks on silicon using in-or near-memory computing techniques (e.g., Brein [35], Conv-RAM [36]) with energy efficiencies in the range 20-55 Top/s/W. Such high energy efficiency and throughput achievable using ASIC accelerators are counterbalanced by limited flexibility, being application specific, which makes them unattractive to satisfy fully the flexibility demand of IoT edge nodes.…”

Section: Related Workmentioning

confidence: 99%

PULP-NN: accelerating quantized neural networks on parallel ultra-low-power RISC-V processors

Garofalo

Rusci

Conti

et al. 2019

Phil. Trans. R. Soc. A.

127

145

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We present PULP-NN, an optimized computing library for a parallel ultra-low-power tightly coupled cluster of RISC-V processors. The key innovation in PULP-NN is a set of kernels for quantized neural network inference, targeting byte and sub-byte data types, down to INT-1, tuned for the recent trend toward aggressive quantization in deep neural network inference. The proposed library exploits both the digital signal processing extensions available in the PULP RISC-V processors and the cluster’s parallelism, achieving up to 15.5 MACs/cycle on INT-8 and improving performance by up to 63 × with respect to a sequential implementation on a single RISC-V core implementing the baseline RV32IMC ISA. Using PULP-NN, a CIFAR-10 network on an octa-core cluster runs in 30 × and 19.6 × less clock cycles than the current state-of-the-art ARM CMSIS-NN library, running on STM32L4 and STM32H7 MCUs, respectively. The proposed library, when running on a GAP-8 processor, outperforms by 36.8 × and by 7.45 × the execution on energy efficient MCUs such as STM32L4 and high-end MCUs such as STM32H7 respectively, when operating at the maximum frequency. The energy efficiency on GAP-8 is 14.1 × higher than STM32L4 and 39.5 × higher than STM32H7, at the maximum efficiency operating point. This article is part of the theme issue ‘Harmonizing energy-autonomous computing and intelligence’.

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Section: Related Workmentioning

confidence: 99%

PULP-NN: accelerating quantized neural networks on parallel ultra-low-power RISC-V processors

Garofalo

Rusci

Conti

et al. 2019

Phil. Trans. R. Soc. A.

127

145

View full text Add to dashboard Cite

show abstract

“…One of the first architectures to exploit these peculiarities has been FINN [28], which is able to reach more than 200 Gop/s/W on a Xilinx FPGA, vastly outperforming the state-of-the-art for FPGA-based deep inference accelerators. Recent efforts for the deployment of binary neural networks on silicon, such as BRein [29], XNOR-POP [30], Conv-RAM [31] and Khwa et al [32] have mainly targeted in-memory computing, with energy efficiencies in the range 20-55 Top/s/W. However, the advantage of this methodology is not yet clear, as more "traditional" ASICs such as UNPU [33] and XNORBIN [34] can reach a similar level of efficiency of 50-100 Top/s/W.…”

Section: Related Workmentioning

confidence: 99%

XNOR Neural Engine: A Hardware Accelerator IP for 21.6-fJ/op Binary Neural Network Inference

Conti¹,

Schiavone²,

Benini³

2018

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

110

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“…In Table IV, we compare the 256 × 256 PPAC with existing hardware accelerators that have been specialized for binarized neural network (BNN) inference and support fully-connected layers [6], [10], [19], [23], [24]. We compare against these designs as their operation closely resembles that of PPAC's 1-bit {±1} MVP operation mode.…”

Section: B Comparison With Existing Acceleratorsmentioning

confidence: 99%

PPAC: A Versatile In-Memory Accelerator for Matrix-Vector-Product-Like Operations

Castañeda

Bobbett

Gallyas-Sanhueza

et al. 2019

2019 IEEE 30th International Conference on Application-Specific Systems, Architectures and Processors (ASAP)

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Processing in memory (PIM) moves computation into memories with the goal of improving throughput and energy-efficiency compared to traditional von Neumann-based architectures. Most existing PIM architectures are either generalpurpose but only support atomistic operations, or are specialized to accelerate a single task. We propose the Parallel Processor in Associative Content-addressable memory (PPAC), a novel in-memory accelerator that supports a range of matrix-vectorproduct (MVP)-like operations that find use in traditional and emerging applications. PPAC is, for example, able to accelerate low-precision neural networks, exact/approximate hash lookups, cryptography, and forward error correction. The fully-digital nature of PPAC enables its implementation with standard-cellbased CMOS, which facilitates automated design and portability among technology nodes. To demonstrate the efficacy of PPAC, we provide post-layout implementation results in 28nm CMOS for different array sizes. A comparison with recent digital and mixed-signal PIM accelerators reveals that PPAC is competitive in terms of throughput and energy-efficiency, while accelerating a wide range of applications and simplifying development.

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BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W

Cited by 136 publications

References 10 publications

PULP-NN: accelerating quantized neural networks on parallel ultra-low-power RISC-V processors

PULP-NN: accelerating quantized neural networks on parallel ultra-low-power RISC-V processors

XNOR Neural Engine: A Hardware Accelerator IP for 21.6-fJ/op Binary Neural Network Inference

PPAC: A Versatile In-Memory Accelerator for Matrix-Vector-Product-Like Operations

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