Bridging a Data-Flow Execution Model to a Lightweight Programming Model

Giorgi, Roberto; Procaccini, Marco

doi:10.1109/hpcs48598.2019.9188183

Cited by 3 publications

(1 citation statement)

References 30 publications

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“…Second, during the realization of this work, we bumped into some limitations of the FRED architecture we used for FPGA acceleration exploiting DPR capabilities: first, its server-based architecture adds context-switch overheads that might be worked around by re-engineering the FRED run-time so to avoid the presence of the FRED daemon in the critical per-acceleration-request path; second, its current static design for plugging acceleration IPs may be tweaked to improve the power consumption of the managed slots while idle. Moreover, in case multiple consecutive tasks are mapped by the optimizer to FPGA accelerators, the current FRED architecture enforces communication among them in software via the FRED daemon, but this interaction might be much faster by re-engineering FRED internals drawing from data-flow principles [36], for example.…”

Section: Discussionmentioning

confidence: 99%

Multi-criteria Optimization of Real-time DAGs on Heterogeneous Platforms under P-EDF

Cucinotta

Amory

Ara

et al. 2024

ACM Trans. Embed. Comput. Syst.

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This paper tackles the problem of optimal placement of complex real-time embedded applications on heterogeneous platforms. Applications are composed of directed acyclic graphs of tasks, with each DAG having a minimum inter-arrival period for its activation requests, and an end-to-end deadline within which all of the computations need to terminate since each activation. The platforms of interest are heterogeneous power-aware multi-core platforms with DVFS capabilities, including big.LITTLE Arm architectures, and platforms with GPU or FPGA hardware accelerators with Dynamic Partial Reconfiguration capabilities. Tasks can be deployed on CPUs using partitioned EDF-based scheduling. Additionally, some of the tasks may have an alternate implementation available for one of the accelerators on the target platform, which are assumed to serve requests in non-preemptive FIFO order. The system can be optimized by: minimizing power consumption, respecting precise timing constraints; maximizing the applications’ slack, respecting given power consumption constraints; or even a combination of these, in a multi-objective formulation. We propose an off-line optimization of the mentioned problem based on mixed-integer quadratic constraint programming (MIQCP). The optimization provides the DVFS configuration of all the CPUs (or accelerators) capable of frequency switching and the placement to be followed by each task in the DAGs, including the software-vs-hardware implementation choice for tasks that can be hardware-accelerated. For relatively big problems, we developed heuristic solvers capable of providing suboptimal solutions in a significantly reduced time compared to the MIQCP strategy, thus widening the applicability of the proposed framework. We validate the approach by running a set of randomly generated DAGs on Linux under SCHED_DEADLINE, deployed onto two real boards, one with Arm big.LITTLE architecture, the other with FPGA acceleration, verifying that the experimental runs meet the theoretical expectations in terms of timing and power optimization goals.

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Section: Discussionmentioning

confidence: 99%

Multi-criteria Optimization of Real-time DAGs on Heterogeneous Platforms under P-EDF

Cucinotta

Amory

Ara

et al. 2024

ACM Trans. Embed. Comput. Syst.

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DRT: A Lightweight Runtime for Developing Benchmarks for a Dataflow Execution Model

Giorgi

Procaccini

Sahebi

2021

Architecture of Computing Systems

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Distributed large-scale graph processing on FPGAs

et al. 2023

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Processing large-scale graphs is challenging due to the nature of the computation that causes irregular memory access patterns. Managing such irregular accesses may cause significant performance degradation on both CPUs and GPUs. Thus, recent research trends propose graph processing acceleration with Field-Programmable Gate Arrays (FPGA). FPGAs are programmable hardware devices that can be fully customised to perform specific tasks in a highly parallel and efficient manner. However, FPGAs have a limited amount of on-chip memory that cannot fit the entire graph. Due to the limited device memory size, data needs to be repeatedly transferred to and from the FPGA on-chip memory, which makes data transfer time dominate over the computation time. A possible way to overcome the FPGA accelerators’ resource limitation is to engage a multi-FPGA distributed architecture and use an efficient partitioning scheme. Such a scheme aims to increase data locality and minimise communication between different partitions. This work proposes an FPGA processing engine that overlaps, hides and customises all data transfers so that the FPGA accelerator is fully utilised. This engine is integrated into a framework for using FPGA clusters and is able to use an offline partitioning method to facilitate the distribution of large-scale graphs. The proposed framework uses Hadoop at a higher level to map a graph to the underlying hardware platform. The higher layer of computation is responsible for gathering the blocks of data that have been pre-processed and stored on the host’s file system and distribute to a lower layer of computation made of FPGAs. We show how graph partitioning combined with an FPGA architecture will lead to high performance, even when the graph has Millions of vertices and Billions of edges. In the case of the PageRank algorithm, widely used for ranking the importance of nodes in a graph, compared to state-of-the-art CPU and GPU solutions, our implementation is the fastest, achieving a speedup of 13 compared to 8 and 3 respectively. Moreover, in the case of the large-scale graphs, the GPU solution fails due to memory limitations while the CPU solution achieves a speedup of 12 compared to the 26x achieved by our FPGA solution. Other state-of-the-art FPGA solutions are 28 times slower than our proposed solution. When the size of a graph limits the performance of a single FPGA device, our performance model shows that using multi-FPGAs in a distributed system can further improve the performance by about 12x. This highlights our implementation efficiency for large datasets not fitting in the on-chip memory of a hardware device.

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Bridging a Data-Flow Execution Model to a Lightweight Programming Model

Cited by 3 publications

References 30 publications

Multi-criteria Optimization of Real-time DAGs on Heterogeneous Platforms under P-EDF

Multi-criteria Optimization of Real-time DAGs on Heterogeneous Platforms under P-EDF

DRT: A Lightweight Runtime for Developing Benchmarks for a Dataflow Execution Model

Distributed large-scale graph processing on FPGAs

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