Bridging fault detection in cluster based FPGA by using Muller C element

Das, Nachiketa; Roy, Pranab; Rahaman, Hafizur

doi:10.1016/j.compeleceng.2013.08.009

Cited by 2 publications

(2 citation statements)

References 12 publications

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“…a flip flop). This method is different from other existing implementations [30,31]. In addition, the output is set to '0' and it does not need initialisation.…”

Section: Majority Tmr Votermentioning

confidence: 99%

Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme

Sheikhpur

Taheri

Ansari³

et al. 2021

IET Computers & Digital Tech

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Digital data transmission is day by day more vulnerable to both malicious and natural faults. With an aim to assure reliability, security and privacy in communication, a low-cost fault resilient architecture for Advanced Encryption Standard (AES) is proposed. In order not to degrade the reliability of our AES architecture, the reliability of voter is very important, for which reason we have introduced a novel voting scheme include a majority voter (named TMR voter) and an error barrier element (named DMR voter). In this paper, a reliable and secure 32-bit data-path AES implementation based on our robust fault resilient approach is developed. We illustrate that the proposed architecture can tolerate up to triple-bit (byte) simultaneous faults at each pipeline stage's logic and verify our claim through extensive error simulations. Error simulation results also show that our architecture achieves close to 100% fault-masking capability for multiple-bit (byte) faults. Finally, it is shown that the Application-Specific Integrated Circuit implementation of the fault-tolerant architectures using the composite field-based S-box, CFB-AES, and ROMbased S-box, RB-AES allows better area usage, throughput and fault resilience trade-off compared to their counterparts. So, it provides the most appropriate features to be used in highly-secure resource-constraint applications.

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“…a flip flop). This method is different from other existing implementations [30,31]. In addition, the output is set to '0' and it does not need initialisation.…”

Section: Majority Tmr Votermentioning

confidence: 99%

Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme

Sheikhpur

Taheri

Ansari³

et al. 2021

IET Computers & Digital Tech

View full text Add to dashboard Cite

show abstract

“…It has been specified formally in 1955 by American mathematician and computer scientist David E. Muller [1]. Implementation of this element in ASIC (Application Specific Integrated Circuits) is widely discussed in many publications, for example [2,3], and many high-performance and reliable circuits and designs exist. Even when containing or implementing multidomain technologies, most of today's FPGA (Field Programmable Gate Arrays) architectures are not designed and ready for implementation of asynchronous systems.…”

Section: Introductionmentioning

confidence: 99%

On implementation and usage of muller C-element in FPGA-based dependable systems

Pfeifer

Vierhaus

2017

2017 International Conference on Applied Electronics (AE)

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Muller C elements are key digital blocks especially used in asynchronous circuits and digital systems and correction of transient (glitch) errors. This paper presents an overview of implementation of Muller C elements in FPGAs. A new scheme is proposed in this paper and the impact of LUT input signal selection is discussed. Finally, unique measurements and experiments performed in Xilinx FPGAs and improved parameters are presented as well.

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Bridging fault detection in cluster based FPGA by using Muller C element

Cited by 2 publications

References 12 publications

Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme

Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme

On implementation and usage of muller C-element in FPGA-based dependable systems

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