This paper presents a novel technique for online testing of feedback bridging faults in the interconnects of the cluster based FPGA. The detection circuit will be implemented using BISTER configuration. We have configured the Block Under Test (BUT) with a pseudo-delay independent asynchronous element known as Muller-C element. Xilinx Jbits 3.0 API (Application Program Interface) is used to implement the BISTER structure in the FPGA. By using Jbits, we can reconfigure dynamically the device, in which the partial bit stream only affects part of the device. In the comparison to the traditional FPGA development tool (ISE), Jbits is faster to map the specific portion of the circuit to a specific tile. We also have more controllability over the utilization of internal resources of FPGA, so that we can perform this partial reconfiguration.14th IEEE International On-Line Testing Symposium 2008 978-0-7695-3264-6/08 $25.00

The recent trend of reconfigurable hardware and convergence of hardware platform in embedded system have enhanced the application of FPGAs. Although the capability and performance of FPGA have advanced, the testing of FPGAs both online and off-line (manufacturer oriented testing) poses a major challenge. Importance of delay testing has grown especially for high-speed circuits. Even presence of small delay fault may cause any critical path to fail. As delay testing, using automatic test equipment is found to be quite expensive; BIST (Built-In-Self-Test) can significantly reduce the cost of delay fault detection without using extra hardware. We have presented a BIST structure to test delay fault of various resources and interconnects of FPGA. The proposed scheme can be implemented for both online as well as off-line testing. We have also proposed a new 3-diagnosable BISTer structure that improves the testing efficiency of our BISTer. The proposed technique can detect the presence of fault, even if all the three units ( TPG, ORA, BUT) in a BIST are faulty. We have simulated our method in Xilinx Vertex-II FPGA, using ISE tool Jbits3.0 API and XHWI (Xilinx Hardware Interface) provided by Xilinx and MATLAB7.0.

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