Build-in-Self-Test of FPGA for diagnosis of delay fault

Abstract

The recent trend of reconfigurable hardware and convergence of hardware platform in embedded system have enhanced the application of FPGAs. Although the capability and performance of FPGA have advanced, the testing of FPGAs both online and off-line (manufacturer oriented testing) poses a major challenge. Importance of delay testing has grown especially for high-speed circuits. Even presence of small delay fault may cause any critical path to fail. As delay testing, using automatic test equipment is found to be quite expensive; BIST (Built-In-Self-Test) can significantly reduce the cost of delay fault detection without using extra hardware. We have presented a BIST structure to test delay fault of various resources and interconnects of FPGA. The proposed scheme can be implemented for both online as well as off-line testing. We have also proposed a new 3-diagnosable BISTer structure that improves the testing efficiency of our BISTer. The proposed technique can detect the presence of fault, even if all the three units ( TPG, ORA, BUT) in a BIST are faulty. We have simulated our method in Xilinx Vertex-II FPGA, using ISE tool Jbits3.0 API and XHWI (Xilinx Hardware Interface) provided by Xilinx and MATLAB7.0.

Built‐in‐self‐test technique for diagnosis of delay faults in cluster‐based field programmable gate arrays

“…The STAR area will move to right by two columns and down by two rows after finishing of the test session. To test an FPGA of (L × M ) size, total {6 × ⌊M/3⌋} configurations are required where M > L. The delay fault of horizontal and vertical wire segments and configurable Interconnect Point (CIP) can be tested by joining both H-STAR and V-STAR [1,14,15]. Several 'wire under test' (WUT) are tested at a time.…”

“…A test pair < v 1 , v 2 > is required to detect the transition fault f on a signal line. The initial vector v 1 must set the target node to an initial value 0 [1] for S‐t‐R [ S‐t‐F] fault. The test vector v 2 has to launch the corresponding transition at the target node and also propagate the fault effect to the primary output.…”

“…Section 2 describes the proposed test method. The implementation of BISTer structure and new full‐diagnosable BIST architecture suitable for testing delay fault and the implementation details are presented in Section 3 [Preliminary version of this work was published in ASQED [1], MWSCAS [2]. ].…”