2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS) 2011
DOI: 10.1109/mwscas.2011.6026578
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New technique for testing of delay fault in cluster based FPGA

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Cited by 1 publication
(2 citation statements)
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“…The method in [15] presents BIST architecture for testing of stuck‐at‐faults, delay faults and bridging faults in FPGA interconnect. The scheme [2, 16] proposes the diagnosis of delay fault for most of the resources of FPGAs. The dynamic delay model of LUT in FPGA has been explained using resistor–capacitor (RC) model [12].…”
Section: Introductionmentioning
confidence: 99%
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“…The method in [15] presents BIST architecture for testing of stuck‐at‐faults, delay faults and bridging faults in FPGA interconnect. The scheme [2, 16] proposes the diagnosis of delay fault for most of the resources of FPGAs. The dynamic delay model of LUT in FPGA has been explained using resistor–capacitor (RC) model [12].…”
Section: Introductionmentioning
confidence: 99%
“…Section 2 describes the proposed test method. The implementation of BISTer structure and new full‐diagnosable BIST architecture suitable for testing delay fault and the implementation details are presented in Section 3 [Preliminary version of this work was published in ASQED [1], MWSCAS [2]. ].…”
Section: Introductionmentioning
confidence: 99%