Bridging Fault Test Method With Adaptive Power Management Awareness

Abstract

Abstract-A key design constraint of circuits used in handheld devices is the power consumption, mainly due to battery life limitations. Adaptive power management (APM) techniques aim to increase the battery life of such devices by adjusting the supply voltage and operating frequency, and thus the power consumption, according to the workload. Testing for resistive bridging defects in APM-enabled designs raises a number of challenges due to their complex analog behavior. Testing at more than one supply voltage setting can be employed to improve defect coverage in such systems, however, switching between several supply voltage settings has a detrimental impact on the overall cost of test. This paper proposes a multi-Vdd automatic test generation method which delivers 100% resistive bridging defect coverage and also a way of reducing the number of supply voltage settings required during test through test point insertion. The proposed techniques have been experimentally validated using a number of benchmark circuits.

Multivoltage Aware Resistive Open Fault Model

“…That is, the full resistance continuum of ROF is divided into intervals and ranges representing distinct delay behaviors and detection thresholds. Though, the concept of dividing the whole resistance continuum into resistance intervals is not new as being practised in [11], [21]. However, in this work the intervalization concept relies on the combined observation of the delay behavior and detectability of the open resistance as far as the supply voltage is concerned.…”

“…After generating the discrete open resistance set (line 1), the procedure starts in the first part by fault simulating all fault locations (ROF s), test patterns (T P s) using V DD settings (V DDs) and open resistance values (ROs) to obtain the path delay information (P D) as shown in lines (3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16)(17)(18). Once the delay values (P D) for fault free paths (∀RO = 0) and faulty paths (∀RO ∈ ROs) are obtained, the longest path delays at each V DD of long paths (LP D G (V DD)) considering (T P ∈ T P s G ) and of short paths (LP D S (V DD)) considering (T P ∈ T P s S ) are identified using the fault free path delay data P D (∀RO = 0) as shown in line [19][20][21][22].…”

“…To optimize the screening and detection of resistive open faults (ROFs), testing methods employing multiple supply voltages have been investigated and proved to give good results [5], [6], [7], [8]. With the emergence of low power designs which utilize multiple supply voltage levels [9], multi-V DD -based methods are ow of critical concern for effective testing and diagnosis [10], [11], [12], [13], [14].…”

Diagnosis of Multiple-Voltage Design With Bridge Defect

“…1-B), we can see that two distinct Logic Faults LF1 and LF2 can be identified for each Vdd setting. However, because the voltage level on the output of D1 does not scale linearly with the input threshold voltages of S1 and S2 when changing the supply voltage, the resistance intervals corresponding to LF1 and LF2 differ from one supply voltage setting to another [19], [20]. Fig.…”

“…The nature of bridge defects in multi-Vdd designs is such that they manifest themselves at one or more voltage settings [18]- [20]. Existing diagnosis techniques use a single Vdd setting and therefore diagnosis for multi-Vdd designs imposes a challenge as bridge defects exhibit supply voltage dependent behavior.…”