Bridging the Gap between Compilation and Synthesis in the DEFACTO System

Abstract. Loop unrolling is the main compiler technique that allows reconfigurable architectures achieve large degrees of parallelism. However, loop unrolling increases the area and can potentially have a negative impact on clock cycle time. In most embedded applications, the critical parameter is the throughput. Loop unrolling can therefore have contradictory effects on the throughput. As a consequence there exists, in general, a degree of unrolling that maximizes the throughput per unit area. This paper studies the effect of loop unrolling on the area, clock speed and throughput within the ROCCC, C to VHDL compilation framework. Our results indicate that due to the unique design of the ROCCC compilation framework, FPGA area either shrinks or increases at a very low rate for the first few times the loops are unrolled. This reduced area causes the clock cycle time to decrease and thus a great gain in throughput. Our results also show that there are different optimal unrolling factors for different programs.

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“…The DEFACTO [16] system takes C as input and generates VHDL code. It allows arbitrary memory accesses within the datapath.…”

Section: Related Workmentioning

confidence: 99%

Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs

Buyukkurt

Zhi

Najjar

2006

Reconfigurable Computing: Architectures and Applications

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“…Figure 4 depicts the set of compiler analyses implemented specifically for our DEFACTO system, a design environment for FPGA-based systems [10]. The SUIF code that is the input to this analysis suite contains data dependence information and also information about each loop nest defined as a unique pipe stage.…”

Section: Compilation System Overviewmentioning

confidence: 99%

“…The latter difference stems from the observation that many, though not all, algorithms mapped to FPGAs have sufficiently small loop bounds or small reuse distances, and the number o f registers that can be configured on an FPGA is sufficiently large, that reuse across multiple loops can be supported. A more detailed description of our scalar replacement and register reuse analysis can be found in [10]. [j] accesses in the first unroll section, each ele ment of array u is loaded into a register, u_0_0, once, and then that value is reused 18 times in each iteration of the inner loop.…”

Section: Reuse Analysis and Scalar Replacementmentioning

confidence: 99%

“…A typical layout is cyclic in at least one dimension of an array, possibly more, but can be block cyclic in the presence of packing and strided accesses. Further discussion of the data layout analysis and transformation can be found in [10].…”

Section: Custom Data Layout and Array Renamingmentioning

confidence: 99%

“…Using these annotations, each stage is translated into behavioral VHDL using a tool we developed in the context of the DEFACTO project [10]. The communication, occurring between each pipe stage, is translated into corresponding host functions that copy data to and from the corresponding memories, if applicable, along with synchronization signals to each FPGA indicating when it is safe to initiate execution.…”

Section: Code Generationmentioning

confidence: 99%

See 2 more Smart Citations

Coarse-grain pipelining on multiple FPGA architectures

Ziegler

Hall

et al.

Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

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Reconfigurable systems, and in particular, FPGA-based custom computing machines, offer a unique opportunity to define application-specific architectures. These architectures offer performance advantages for application domains such as image processing, where the use of customized pipelines exploits the inherent coarse-grain parallelism. In this paper we describe a set of program analyses and an implementation that map a sequential and un-annotated C program into a pipelined implementation running on a set of FPGAs, each with multiple external memories. Based on well-known parallel computing analysis techniques, our algorithms perform unrolling for operator parallelization, reuse and data layout for memory parallelization and precise communication analysis. We extend these techniques for FPGA-based systems to automatically partition the application data and computation into custom pipeline stages, taking into account the available FPGA and interconnect resources. We illustrate the analysis components by way of an example, a machine vision program. We present the algorithm results, derived with minimal manual intervention, which demonstrate the potential of this approach for automatically deriving pipelined designs from high-level sequential specifications.

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Applied Reconfigurable Computing

Cardoso¹

2019

Lecture Notes in Computer Science

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Bridging the Gap between Compilation and Synthesis in the DEFACTO System

Cited by 31 publications

References 8 publications

Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs

Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs

Coarse-grain pipelining on multiple FPGA architectures

Applied Reconfigurable Computing

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