Broadband esd protection circuits in cmos technology

Galal, Shereen M.; Razavi, Behzad

doi:10.1109/jssc.2003.818568

Cited by 120 publications

(22 citation statements)

References 3 publications

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“…Under the conditions given by (2)- (3), it can be proved that Z IN = R T at all frequencies [5,8]. Fig.…”

Section: Analysis Of Conventional T-coilsmentioning

confidence: 90%

“…The on-chip inductors generally occupy large areas on the top metal layers that are supposed to be used for power delivery. For example, in [5] two cross coupled 1nH inductors have 85 μm×85 μm area. Large inductors may deteriorate not only area efficiency but also power integrity.…”

Section: Analysis Of Conventional T-coilsmentioning

confidence: 99%

“…2 has been used in part of ESD protection structures [4,5]. The T-coil network has the shunt-series inductive peaking structure which has been commonly used in microwave engineering [6].…”

Section: Introductionmentioning

confidence: 99%

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Design of a Reliable Broadband I/O Employing T-coil

Kim¹,

Kim²,

Jung³

et al. 2009

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Inductive peaking using T-coils has been widely used in broadband I/O interfaces. In this paper, we analyze technical effects and limitations of the T-coil, and discuss several methods that can overcome these restrictions and improve the practicality of the T-coil. In particular we also propose and verify a circuit topology which can further extend bandwidth beyond the limit that conventional T-coil can achieve, and transfer 20 Gb/s data without noticeable distortion.

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“…Under the conditions given by (2)- (3), it can be proved that Z IN = R T at all frequencies [5,8]. Fig.…”

Section: Analysis Of Conventional T-coilsmentioning

confidence: 90%

Section: Analysis Of Conventional T-coilsmentioning

confidence: 99%

See 1 more Smart Citation

Design of a Reliable Broadband I/O Employing T-coil

Kim¹,

Kim²,

Jung³

et al. 2009

JSTS:Journal of Semiconductor Technology and Science

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“…For example, the capacitive impedance discontinuity due to PTH (plated through-hole) is neutralized with an inductive discontinuity, such as a thin line segment adjacently placed to the PTH. However, such techniques do not resolve the impedance discontinuity at the silicon/package interface caused by the I/O buffer's parasitic capacitance which significantly degrades the signal transmission performance [4], [5]. Moreover, because low-cost consumer device packages are generally substantially smaller than the high-end device pcakges [3], there is not always enough space to incorporate additional counter impedance discontinuities for neutralizing existing impedance discontinuities.…”

Section: Introductionmentioning

confidence: 99%

A low-cost wire-bonding package design with package built-in three-dimensional distributed matching circuit for over 5Gbps SerDes applications

Oikawa

2009

2009 59th Electronic Components and Technology Conference

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compensates for the impedance difference between the silicon I/O buffer and the system board. A package built-in threedimensional distributed matching circuit technique [1], which had originally been developed for FCBGA, has been extended and adapted for use in the low-cost wire-bonding packages. The matching circuit discussed in this paper consists of only the parasitic R/L/G/C (resistance/ inductance/ conductance/ capacitance) components distributed three-dimensionally along the signal line in the conventional package substrate and bonding wire. Thus there is no need for any additional manufacturing process, which keeps down the production cost of the high-speed consumer devices.Another important aspect of the low-cost wire-bonding package is a signal-power coupling effect [6]. This effect has recently been discussed when analyzing the SSN (simultaneous switching noise) or SSO (simultaneous switching output) of the memory devices such as DDR2/DDR3. However, the effect on the high-speed SerDes signal performance has rarely been discussed.Because of bonding wires and many ground inconsistencies inside the low-cost wire-bonding packages, the signals are easily coupled with the power supply which acts as a non-ideal secondary return path. This secondary return path strongly affects the signal performance in the over 5Gbps region. This paper analyzes the signal-power coupling effect on the high-speed SerDes device for the first time based on the full-wave, full-3D, signal-power-combined electromagnetic analysis. Matching circuit design for the wire-bonding packagesThe fundamental concept of the package built-in threedimensional distributed matching circuit[1] is composed of following two ideas. The first is to control parasitic capacitance nearby signal line distributed three-dimensionally. The second is to control the signal phase difference between the silicon device pin-out and the above controlled parasitic capacitance. In other words, it intentionally uses the phase difference of the traveling electromagnetic wave along the signal line. Therefore, the design is easier for high frequency or high-speed devices which signal phase difference is larger than low frequency or low-speed devices. Fig.1 illustrates an impedance chart for the S-parameters of typical I/O buffer with red line and the transmission line with intermediate capacitance at location L. Because of parasitic capacitance, the impedance of I/O buffer is low and capacitive, which is to be compensated with the signal AbstractThe package built-in three-dimensional distributed matching circuit[1], which had been developed for FCBGA , has been extended to the low-cost wire-bonding packages. The two-metal layer package designed for 6.4Gps SerDes (Serializer-Deserializer) achieved a ~4dB return loss improvement as well as better signal waveform compared to the normal 50-Ohm design. In addition, signal-power coupling effect on the high-speed SerDes device has been analyzed for the first time based on the full-wave, full-3D, signal-powercombined electromagneti...

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“…For narrowband RF applications, cancellation or isolation can be used [3]. Broadband RF ESD protection concepts implementing a T-coil [4] or distributed protection elements have been proposed, but they suffer from large area consumption and delicate dimensioning. Alternatively bootstrapping can be applied to screen out parasitic capacitances [5].…”

mentioning

confidence: 99%

A 10GHz Broadband Amplifier with Bootstrapped 2kV ESD Protection

Soldner

Kim

Streibl

et al. 2007

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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ESD designers have to consider two shrinking design windows. On one hand, the oxide breakdown voltage of a thin-oxide transistor melted down from 12V in a 0.25µm technology to 4.5V at the 90nm node. On the other hand, the continuing demand for narrowband and broadband communication systems pushes the carrier frequencies (e.g. up to 10GHz for UWB). This reduces the tolerable capacitive load of the ESD elements. To guarantee a 2kV human body model (HBM) target, the state of the art ESD protection concepts require parasitic capacitances in the order of 100 to 150fF. This capacitive load leads to an extrapolated frequency limit of about 5GHz [1].To bridge the gap from 5GHz to frequencies >10GHz, where the implementation of shunting coils makes ESD design easier [2], the parasitic ESD capacitance can be eliminated by several compensation techniques. For narrowband RF applications, cancellation or isolation can be used [3]. Broadband RF ESD protection concepts implementing a T-coil [4] or distributed protection elements have been proposed, but they suffer from large area consumption and delicate dimensioning. Alternatively bootstrapping can be applied to screen out parasitic capacitances [5]. Here, a mid node is created by arranging two ESD elements in series as exemplarily shown in Fig. 30.7.1. If an additional sense-amplifier circuit mirrors the RF signal from the RF pad to the mid node without a time shift ∆t, no displacement current will flow over the ESD element connected to the pad. Thus, the parasitic ESD capacitance is compensated. For frequencies of ~10MHz as investigated in [5], a simple source follower could uphold the requirement ∆t→0.This work introduces a low-C ESD-protection element, referred to as dual-diode silicon-controlled rectifier (DD-SCR), with a parasitic capacitance of ~50fF, bypassing the need to cascode the ESD device for bootstrapping. The functional principle of the DD-SCR is shown in the left part of Fig. 30.7.2. It is based on a transient triggered silicon controlled rectifier (TT-SCR) as described in [1]. For a positive stress at pad 1 against V DD (abbr. PAD(pos)V DD ), the ESD current flows along the dashed-dotted line over two forwardbiased PN junctions. For a PAD(pos)V SS stress, the main discharge current will flow along the dashed line. To guarantee this, the thyristor has to be turned on by an initial trigger current through the base of the first PNP transistor of the SCR. This trigger current will flow via the forward-biased D1 and the blocking capacitance C b to ground (dotted line). The negative discharges make use of the SCR from pad1 to V DD accordingly. Adding D1 to the thyristor has 2 benefits: first, the parasitic capacitance of the SCR, that is dominated by the first PN junction at the RF pad, is reduced; secondly, the required mid-node for the bootstrap concept is created without the need of cascoding the whole ESD device.On the right side of Fig. 30.7.2, a bootstrapped version of a DD-SCR protection circuit is shown (for simplification the second thyristor is not shown...

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Broadband esd protection circuits in cmos technology

Cited by 120 publications

References 3 publications

Design of a Reliable Broadband I/O Employing T-coil

Design of a Reliable Broadband I/O Employing T-coil

A low-cost wire-bonding package design with package built-in three-dimensional distributed matching circuit for over 5Gbps SerDes applications

A 10GHz Broadband Amplifier with Bootstrapped 2kV ESD Protection

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